Search results for "Susmita Sur-Kolay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Susmita Sur-Kolay, Swarup Bhunia	Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Debasri Saha, Susmita Sur-Kolay	SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay	Floorplanning for Partially Reconfigurable FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Amlan Chakrabarti, Susmita Sur-Kolay, Ayan Chaudhury	Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning	CoRR	2011	DBLP BibTeX RDF
1	Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay	Cone-based placement for field programmable gate arrays.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay	TSV-aware Scan Chain Reordering for 3D IC.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey	Test pattern generation for droop faults.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Debasri Saha, Susmita Sur-Kolay	Robust intellectual property protection of VLSI physical design.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Debasri Saha, Susmita Sur-Kolay	A Unified Approach for IP Protection across Design Phases in a Packaged Chip.	VLSI Design	2010	DBLP DOI BibTeX RDF	embedding of signature, observabality, scan tree architecture, Design-for-Testability, Intellectual Property Protection
1	Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee	FPGA placement using space-filling curves: Theory meets practice.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF
1	Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay	MAkE: Multiobjective algorithm for k-way equipartitioning of a point set.	Appl. Soft Comput.	2009	DBLP DOI BibTeX RDF
1	Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu	Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Susmita Sur-Kolay, Satyajit Banerjee, S. Mukhopadhyaya, C. A. Murthy	The Double Digest Problem: finding all solutions.	IJBRA	2009	DBLP DOI BibTeX RDF
1	Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Droop sensitivity of stuck-at fault tests.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Debasri Saha, Susmita Sur-Kolay	Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Debasri Saha, Susmita Sur-Kolay	Encoding of Floorplans through Deterministic Perturbation.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay	Floorplanning for Partial Reconfiguration in FPGAs.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das	Hierarchical partitioning of VLSI floorplans by staircases.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	balanced bipartitioning, NP-completeness, Floorplanning, network flow, global routing
1	Amlan Chakrabarti, Susmita Sur-Kolay	Nearest Neighbour based Synthesis of Quantum Boolean Circuits.	Engineering Letters	2007	DBLP BibTeX RDF
1	Debasri Saha, Susmita Sur-Kolay	Fast Robust Intellectual Property Protection for VLSI Physical Design.	ICIT	2007	DBLP DOI BibTeX RDF	fingerprint- ing, VLSI physical design, watermarking, Intellectual property, electronic design automation
1	Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma	A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.	ICCTA	2007	DBLP DOI BibTeX RDF
1	Pritha Banerjee, Susmita Sur-Kolay	Faster Placer for Island-Style FPGAs.	ICCTA	2007	DBLP DOI BibTeX RDF
1	Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu	Floorplanning in Modern FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta	Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI.	ICIT	2006	DBLP DOI BibTeX RDF	balanced partitioning, low power clock trees in nanometer chips, genetic algorithm, cluster analysis, Multiobjective optimization
1	Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu	Test Pattern Generation for Power Supply Droop Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy	Fast FPGA Placement using Space-filling Curve.	FPL	2005	DBLP BibTeX RDF
1	Susmita Sur-Kolay, Satyajit Banerjee, S. Mukhopadhyaya, C. A. Murthy	Genetic Algorithm for Double Digest Problem.	PReMI	2005	DBLP DOI BibTeX RDF
1	Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty	Hot Spots and Zones in a Chip: A Geometrician's View.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Manhattan-diagonal routing in channels and switchboxes.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Manhattan routing, channel density, diagonal wires
1	Sanjay Goswami, Susmita Sur-Kolay	Virtual Molecular Computing - Emulating DNA Molecules.	IWDC	2004	DBLP DOI BibTeX RDF
1	Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah	Physical Design Trends and Layout-Based Fault Modeling. (PDF / PS)	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang	A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.	DATE	2004	DBLP DOI BibTeX RDF
1	Susmita Sur-Kolay, Satyajit Banerjee, C. A. Murthy	Flavours of Traveling Salesman Problem in VLSI Design.	IICAI	2003	DBLP BibTeX RDF
1	Parthasarathi Dasgupta, Susmita Sur-Kolay	Slicible rectangular graphs and their optimal floorplans.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	graph dualization, nonslicible floorplans, slicible floorplans, heuristic search, planar graphs, Floorplanning
1	Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay	Combined instruction and loop parallelism in array synthesis for FPGAs.	ISSS	2001	DBLP BibTeX RDF
1	Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta	Partitioning Routing Area into Zones with Distinct Pins.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy	Area(number)-balanced hierarchy of staircase channels with minimum crossing nets.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
1	Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay	Optimal Partitioning for FPGA Based Regular Array Implementations.	PARELEC	2000	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Topological Routing Amidst Polygonal Obstacles.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	A unified approach to topology generation and optimal sizing of floorplans.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.	VLSI Design	1998	DBLP DOI BibTeX RDF	nonslicible floorplan, switchbox, Manhattan-diagonal model, channel, VLSI routing
1	Parthasarathi Dasgupta, Susmita Sur-Kolay	Slicibility of rectangular graphs and floorplan optimization.	ISPD	1997	DBLP DOI BibTeX RDF	graph dualization, nonslicible floorplans, slicible floorplans, very large scale integration, heuristic search, planar graphs, floorplanning
1	P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	VLSI floorplan generation and area optimization using AND-OR graph search.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph
1	Abhik Roychoudhury, Susmita Sur-Kolay	Efficient Algorithms for Vertex Arboricity of Planar Graphs.	FSTTCS	1995	DBLP DOI BibTeX RDF	Vertex arboricity, testing of sequential circuits, graph coloring, planar graph
1	Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	A unified approach to topology generation and area optimization of general floorplans.	ICCAD	1995	DBLP DOI BibTeX RDF	VLSI floorplanning, AND-OR graphs, placement, heuristic search
1	Susmita Sur-Kolay, Bhargab B. Bhattacharya	Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning.	DAC	1992	DBLP BibTeX RDF
1	Susmita Sur-Kolay, Bhargab B. Bhattacharya	The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order.	ICCD	1991	DBLP BibTeX RDF
1	Susmita Sur-Kolay, Bhargab B. Bhattacharya	Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning.	FSTTCS	1988	DBLP DOI BibTeX RDF	plane triangulated graphs, rectangular duals, slicing structures, algorithms, floorplanning, VLSI layout

Publications of "Susmita Sur-Kolay" ( http://dblp.L3S.de/Authors/Susmita_Sur-Kolay )