Search results for "Swaroop Ghosh"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Swaroop Ghosh, Kaushik Roy	Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy	Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy	Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy	Coping with Variations through System-Level Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	JETC	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
1	Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy	O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Kaushik Roy	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Patrick Ndai, Kaushik Roy	A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.	DATE	2008	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jing Li, Swaroop Ghosh, Kaushik Roy	A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs.	ITC	2007	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.	DATE	2007	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.	DAC	2006	DBLP DOI BibTeX RDF	adaptive source biasing, hold failures, low power SRAM
1	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.	IOLTS	2006	DBLP DOI BibTeX RDF	Test-per-scan BIST, delay sensor, fault diagnosis, fault localization, test point insertion
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das	A built-in self-testing method for embedded multiport memory arrays.	IEEE T. Instrumentation and Measurement	2005	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy	A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.	IOLTS	2005	DBLP DOI BibTeX RDF	Speed binning, delay measurement hardware, process variation
1	Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang	Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh	Embedded core test generation using broadcast test architecture and netlist scrambling.	IEEE Transactions on Reliability	2003	DBLP DOI BibTeX RDF

Publications of "Swaroop Ghosh" ( http://dblp.L3S.de/Authors/Swaroop_Ghosh )