| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kamran Rahmani, Prabhat Mishra, Swarup Bhunia |
Memory-based computing for performance and energy improvement in multicore architectures.  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia |
SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Susmita Sur-Kolay, Swarup Bhunia |
Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang, Somnath Paul, Swarup Bhunia |
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Anandaroop Ghosh, Somnath Paul, Swarup Bhunia |
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia |
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Seetharam Narasimhan, Hillel J. Chiel, Swarup Bhunia |
Ultra-Low-Power and Robust Digital-Signal-Processing Hardware for Implantable Neural Interface Microsystems. |
IEEE Trans. Biomed. Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Swarup Bhunia |
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Swarup Bhunia |
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswin Raghav Krishna, Seetharam Narasimhan, Xinmu Wang, Swarup Bhunia |
MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array. |
CHES |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Keerthi Kunaparaju, Seetharam Narasimhan, Swarup Bhunia |
VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Seetharam Narasimhan, Xinmu Wang, Dongdong Du, Rajat Subhra Chakraborty, Swarup Bhunia |
TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection. |
HOST |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Francis G. Wolff, Srihari Rajgopal, Te-Hao Lee, Mehran Mehregany, Swarup Bhunia |
High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Subidh Ali, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Swarup Bhunia |
Multi-level attacks: An emerging security concern for cryptographic hardware. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia |
Embedded Software Security through Key-Based Control Flow Obfuscation. |
InfoSecHiComNet |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Tatini Mal-Sarkar, Swarup Bhunia |
Sequential hardware Trojan: Side-channel aware design and placement. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia |
A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Hamid Mahmoodi, Swarup Bhunia |
Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tatini Mal-Sarkar, Swarup Bhunia |
Collaborative Trust: A Novel Paradigm of Trusted Mobile Computing |
CoRR |
2010 |
DBLP BibTeX RDF |
|
| 1 | Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Rahul Rao |
Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair. |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Swarup Bhunia |
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
narrow-width operand, superscalar processor, within-die variation |
| 1 | Swarup Bhunia, Anand Raghunathan |
Special session 11B: Hot topic hardware security: Design, test and verification issues. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Seetharam Narasimhan, David R. McIntyre, Francis G. Wolff, Yu Zhou, Daniel J. Weyer, Swarup Bhunia |
A supply-demand model based scalable energy management system for improved energy utilization efficiency. |
Green Computing Conference |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty, Swarup Bhunia |
Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection. |
CHES |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
resgister transfer level (RTL), Hardware Security, IP protection |
| 1 | Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia |
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. |
HOST |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia |
Trustworthy computing in a multi-core system using distributed scheduling. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
A study of asynchronous design methodology for robust CMOS-nano hybrid system design. |
JETC |
2009 |
DBLP DOI BibTeX RDF |
CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines |
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia |
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia |
Hardware Trojan: Threats and emerging solutions. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia |
MERO: A Statistical Approach for Hardware Trojan Detection. |
CHES |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia |
Dynamic Evaluation of Hardware Trust. |
HOST |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP. |
HOST |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
A variation-aware preferential design approach for memory based reconfigurable computing. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia |
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
Security against hardware Trojan through a novel application of design obfuscation. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy |
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
Variable-cycle functional unit, speed binning, Scheduling, process variation, Superscalar Processors |
| 1 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy |
Profit Aware Circuit Design Under Process Variations Considering Speed Binning. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy |
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing |
| 1 | Yu Zhou, Somnath Paul, Swarup Bhunia |
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Diode-resistor logic, CMOSNano, Asynchronous design |
| 1 | Swarup Bhunia, Kaushik Roy |
Low power design under parameter variations. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia |
On-die CMOS voltage droop detection and dynamiccompensation. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
di/dt voltage droop, on-die voltage droop compensation, power supply droop, predictive current injection |
| 1 | Somnath Paul, Swarup Bhunia |
Reconfigurable computing using content addressable memory for improved performance and resource usage. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
field programmable gate array (FPGA), content addressable memory, resource utilization |
| 1 | Seetharam Narasimhan, Somnath Paul, Swarup Bhunia |
Collective computing based on swarm intelligence. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
collective intelligence, adaptive computing, multi-processor |
| 1 | Somnath Paul, Swarup Bhunia |
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia |
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
Diode-resistor logic, logic-level degradation, nano-crossbar circuit, robust circuit design |
| 1 | Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia |
On-Demand Transparency for Improving Hardware Trojan Detectability. |
HOST |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhou, Somnath Paul, Swarup Bhunia |
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty |
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lawrence Leinweber, Swarup Bhunia |
Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Kaushik Roy |
Low power design under parameter variations. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
STTRAM, emerging memory technologies, nonvolatile FPGA |
| 1 | Rajat Subhra Chakraborty, Swarup Bhunia |
Hardware protection and authentication through netlist level obfuscation. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
IP piracy, design for security, hardware authentication, hardware obfuscation, hardware protection |
| 1 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
Low-Power and testable circuit synthesis using Shannon decomposition. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power |
| 1 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy |
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy |
Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia |
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Kaushik Roy |
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhou, Shijo Thekkel, Swarup Bhunia |
Low power FPGA design using hybrid CMOS-NEMS approach. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
hybrid CMOS-NEMS, low power, FPGA design |
| 1 | Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab |
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current |
| 1 | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
scan-based DFT, security, detection probability, low overhead, cryptographic hardware |
| 1 | Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
Process Variations and Process-Tolerant Design. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy |
Tolerance to Small Delay Defects by Adaptive Clock Stretching. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia |
Low-overhead design technique for calibration of maximum frequency at multiple operating points. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
frequency calibration, voltage sensitivity, dynamic voltage and frequency scaling, ring oscillator |
| 1 | Somnath Paul, Swarup Bhunia |
Memory based computation using embedded cache for processor yield and reliability improvement. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy |
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi |
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy |
Speed binning aware design methodology to improve profit under parameter variations. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy |
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia |
Low power synthesis of dynamic logic circuits using fine-grained clock gating. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy |
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy |
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
Test-per-scan BIST, delay sensor, fault diagnosis, fault localization, test point insertion |
| 1 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy |
Synthesis of application-specific highly efficient multi-mode cores for embedded systems. |
ACM Trans. Embedded Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, high level synthesis, synthesis, Digital signal processing (DSP), application specific integrated circuits (ASIC), reconfigurable system |
| 1 | Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy |
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
Asynchronous/synchronous operations, fault tolerance, energy-aware systems, algorithms implemented in hardware |
| 1 | Swarup Bhunia, Kaushik Roy |
A novel wavelet transform-based transient current analysis for fault detection and localization. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy |
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy |
Low-power scan design using first-level supply gating. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy |
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy |
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
Defect Oriented Testing (DOT), dynamic supply current (IDD), wavelet transform, Fourier transform |
| 1 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy |
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
analog filter, trim bit, dynamic supply current (IDD), wavelet transform, frequency response |
| 1 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy |
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy |
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy |
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
process variation, yield, leakage, dual-Vt, metal gate |
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy |
A novel synthesis approach for active leakage power reduction using dynamic supply gating. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy |
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
Failure mechanixm, Process Variation, DFT, SRAM, March Test |
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy |
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
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