Search results for "Syed Rafay Hasan"

Found 8 publication records. Showing 8 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Zaid Al-bayati, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria	A novel hybrid FIFO asynchronous clock domain crossing interfacing method.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs.	Integration	2011	DBLP DOI BibTeX RDF
1	Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria	SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.	ICECS	2011	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Bill Pontikakis, Yvon Savaria	An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs).	ISCAS	2009	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Yvon Savaria	Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili	Optimal partitioning of globally asychronous locally synchronous processor arrays.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	VLSI, partitioning, power optimization, GALS

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Publications of "Syed Rafay Hasan" ( http://dblp.L3S.de/Authors/Syed_Rafay_Hasan )