Search results for "Sying-Jyan Wang"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Tung-Hua Yeh, Sying-Jyan Wang	Power-Aware High-Level Synthesis With Clock Skew Management.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Tung-Hua Yeh, Sying-Jyan Wang	Thermal Safe High Level Test Synthesis for Hierarchical Testability.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Tung-Hua Yeh	High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Katherine Shu-Min Li, Shih-Cheng Chen, Huai-Yan Shiu, Yun-Lung Chu	Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li	Low Peak Power ATPG for n-Detection Test.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang	Level Converting Scan Flip-flops.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li	Layout-aware scan chain reorder for launch-off-shift transition test coverage.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	scan chain ordering, test generation, transition faults, Scan test
1	Po-Chang Tsai, Sying-Jyan Wang	Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li	Design and analysis of skewed-distribution scan chain partition for improved test data compression.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh	Test Data Compression for Minimum Test Application Time.	J. Inf. Sci. Eng.	2007	DBLP BibTeX RDF
1	Sying-Jyan Wang, Tung-Hua Yeh	High-level test synthesis for delay fault testability.	DATE	2007	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li	Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Yu-Hsuan Fu, Sying-Jyan Wang	Test Data Compression with Partial LFSR-Reseeding.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Mingchen Wen, Sying-Jyan Wang, Yen-Nan Lin	Low power parallel multiplier with column bypassing.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu	Low Power BIST with Smoother and Scan-Chain Reorder .	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Yu-Lung Hsu, Sying-Jyan Wang	Retiming-based logic synthesis for low-power.	ISLPED	2002	DBLP DOI BibTeX RDF	switching actvity, low-power, logic design, retiming
1	Nan-Cheng Li, Sying-Jyan Wang	A Reseeding Technique for LFSR-Based BIST Applications.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Reseedling, LFST, BIST, Test Pattern Generator, Pseudo-Random Testing
1	Sying-Jyan Wang	Distributed Diagnosis in Multistage Interconnection Networks.	J. Parallel Distrib. Comput.	2001	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Sheng-Nan Chiou	Generating Efficient Tests for Continuous Scan.	DAC	2001	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Chia-Chun Lien	Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches.	J. Inf. Sci. Eng.	2000	DBLP BibTeX RDF
1	Sying-Jyan Wang, Chen-Jung Wei	Efficient built-in self-test algorithm for memory.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
1	Sying-Jyan Wang, Chao-Neng Huang	Testing and Diagnosis of Interconnect Structures in FPGAs.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang	Distributed Routing in a Fault-Tolerant Multistage Interconnection Network.	Inf. Process. Lett.	1997	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Tsi-Ming Tsai	Test and diagnosis of fault logic blocks in FPGAs.	ICCAD	1997	DBLP DOI BibTeX RDF	FPGA, Test, Diagnosis, BIST
1	Sying-Jyan Wang	Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing.	J. Parallel Distrib. Comput.	1996	DBLP DOI BibTeX RDF
1	Po-Ching Hsu, Sying-Jyan Wang	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
1	Sying-Jyan Wang, Niraj K. Jha	Algorithm-Based Fault Tolerance for FFT Networks.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	FFT networks, system-level fault tolerance technique, reliability, fault tolerant computing, fast Fourier transforms, high throughput, algorithm-based fault tolerance
1	Sying-Jyan Wang	Synthesis of Sequential Machines with Reduced Testing Cost.	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
1	Niraj K. Jha, Sying-Jyan Wang	Design and synthesis of self-checking VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka	Multiple Input Bridging Fault Detection in CMOS Sequential Circuits.	ICCD	1992	DBLP BibTeX RDF
1	Niraj K. Jha, Sying-Jyan Wang	Design and Synthesis of Self-Checking VLSI Circuits and Systems.	ICCD	1991	DBLP BibTeX RDF

Publications of "Sying-Jyan Wang" ( http://dblp.L3S.de/Authors/Sying-Jyan_Wang )