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Results
Found 19 publication records. Showing 19 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Kostas Peppas, Fotis I. Lazarakis, Dimitrios I. Axiotis, Tareq Al-Gizawi, Antonis Alexandridis |
System level performance evaluation of MIMO and SISO OFDM-based WLANs.  |
Wireless Networks  |
2009 |
DBLP DOI BibTeX RDF |
OFDM wireless LANs, Optimal power allocation, Link-to-system-interface, System level performance evaluation, MIMO systems |
| 2 | Frederico De Faria, Marius Strum, Wang Jiang Chau |
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling.  |
ISVLSI  |
2007 |
DBLP DOI BibTeX RDF |
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| 2 | Stefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr |
On core and more: a design perspective for systems-on-a-chip.  |
ASAP  |
1997 |
DBLP DOI BibTeX RDF |
design perspective, highly competitive telecommunications market, system level performance evaluation, computational complexity, system design, systems-on-a-chip, intellectual property, design environment, HW/SW co-design, fast simulation |
| 1 | Hajer Krichene Zrida, Abderrazek Jemai, Ahmed C. Ammari, Mohamed Abid |
System-Level Performance Evaluation of Very High Complexity Media Applications : A H264/AVC Encoder Case Study.  |
IJCNS  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Vasken Genc, Seán Murphy, John Murphy, Abdelhamid Nafaa |
System-Level Performance Evaluation of Multi-Cell Transparent Mode Relay 802.16j Systems.  |
GLOBECOM  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Agisilaos Papadogiannis, George C. Alexandropoulos |
System level performance evaluation of dynamic relays in cellular networks over Nakagami-m fading channels.  |
PIMRC  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Andy D. Pimentel |
The Artemis workbench for system-level performance evaluation of embedded systems.  |
IJES  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Jose F. Monserrat, Rubén Fraile, Daniel Calabuig, Narcís Cardona |
Complete Shadowing Modeling and its Effect on System Level Performance Evaluation.  |
VTC Spring  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Carmen B. Rodríguez-Estrello, Felipe A. Cruz-Pérez, Genaro Hernández-Valdez |
On the system-level statistical characterization of link unreliability in cellular networks.  |
PIMRC  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Mohamad Assaad, Alain Mourad |
New Frequency-Time Scheduling Algorithms for 3GPP/LTE-like OFDMA Air Interface in the Downlink.  |
VTC Spring  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Andrés Rico-Páez, Carmen B. Rodríguez-Estrello, Felipe A. Cruz-Pérez, Genaro Hernández-Valdez |
Queueing Analysis of Mobile Cellular Networks Considering Wireless Channel Unreliability and Resource Insufficiency.  |
International Teletraffic Congress  |
2007 |
DBLP DOI BibTeX RDF |
link unreliability, channel holding time, phase-type probability distributions, queueing analysis, Mobile cellular networks |
| 1 | Ling Luo, Jianjun Yang, Kangsheng Chen |
System-level performance evaluation of UMTS with multi-service.  |
Computer Communications  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Paul Marinier, Angelo Cuffaro, Athmane Touag |
System-Level Performance Evaluation of HSDPA/HSUPA with TCP-Based Application.  |
VTC Fall  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Andy D. Pimentel, Cagkan Erbas, Simon Polstra |
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels.  |
IEEE Trans. Computers  |
2006 |
DBLP DOI BibTeX RDF |
simulation, real-time and embedded systems, modeling techniques, performance analysis and design aids, Modeling of computer architecture |
| 1 | Rolf Enzler, Christian Plessl, Marco Platzner |
System-level performance evaluation of reconfigurable processors.  |
Microprocessors and Microsystems  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Joseph E. Coffland, Andy D. Pimentel |
A Software Framework for Efficient System-level Performance Evaluation of Embedded Systems.  |
SAC  |
2003 |
DBLP BibTeX RDF |
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| 1 | Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu |
An Object-Oriented Design Process for System-on-Chip Using UML.  |
ISSS  |
2002 |
DBLP DOI BibTeX RDF |
system level performance evaluation, UML, design process, system level design, object-oriented analysis and design |
| 1 | Arifur Rahman, Rafael Reif |
System-level performance evaluation of three-dimensional integrated circuits.  |
IEEE Trans. VLSI Syst.  |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | M. D. Canon, D. H. Fritz, John H. Howard, T. D. Howell, Michael F. Mitoma, Juan Rodriguez-Rossel |
A Virtual Machine Emulator for Performance Evaluation (Summary).  |
SOSP  |
1979 |
DBLP DOI BibTeX RDF |
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