Search results for "TLB performance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Jinzhan Peng, Guei-Yuan Lueh, Gansha Wu, Xiaogang Gou, Ryan Rakvic	A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	TLB performance, Java, embedded system
2	Vincent Loechner, Benoît Meister, Philippe Clauss	Data Sequence Locality: A Generalization of Temporal Locality.	Euro-Par	2001	DBLP DOI BibTeX RDF	cache and TLB performance, parameterized polyhedra, Ehrhart polynomials, Memory hierarchy, temporal locality, loop nests
2	Madhusudhan Talluri, Mark D. Hill	Surpassing the TLB Performance of Superpages with Less Operating System Support.	ASPLOS	1994	DBLP DOI BibTeX RDF
1	Abhishek Bhattacharjee, Margaret Martonosi	Inter-core cooperative TLB for chip multiprocessors.	ASPLOS	2010	DBLP DOI BibTeX RDF	parallelism, prefetching, translation lookaside buffer
1	Joshua Magee, Apan Qasem	A case for compiler-driven superpage allocation.	ACM Southeast Regional Conference	2009	DBLP DOI BibTeX RDF
1	Rupak Samanta, Jason Surprise, Rabi N. Mahapatra	Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Chengliang Zhang, Martin Hirzel	Online Phase-Adaptive Data Layout Selection.	ECOOP	2008	DBLP DOI BibTeX RDF
1	Omesh Tickoo, Hari Kannan, Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer, Donald Newell	qTLB: Looking Inside the Look-Aside Buffer.	HiPC	2007	DBLP DOI BibTeX RDF
1	Scott Schneider, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Scalable locality-conscious multithreaded memory allocation.	ISMM	2006	DBLP DOI BibTeX RDF	synchronization-free, shared memory, multithreading, memory management, non-blocking
1	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Tiling, Block Data Layout, and Memory Hierarchy Performance.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	Block data layout, TLB misses, memory hierarchy, tiling, cache misses
1	Huiyang Zhou, Thomas M. Conte	Code Size Efficiency in Global Scheduling for ILP Processors.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	Code Size Efficiency, I-cache Performance, Code Replication, Tail Duplication, Optimal Code Size Efficiency, Diminishing Returns, Quantitative Measure, Instruction Level Parallelism (ILP)
1	David Channon, David Koch	Performance Analysis of Re-configurable Partitioned TLBs.	HICSS	1997	DBLP DOI BibTeX RDF	Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation
1	Rafael H. Saavedra, Alan Jay Smith	Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	execution time prediction, processor caches, table lookaside buffers, Performance evaluation, memory hierarchy
1	Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest	Trap-driven Simulation with Tapeworm II.	ASPLOS	1994	DBLP DOI BibTeX RDF	trap-driven simulation, cache, trace-driven simulation, memory system, TLB
1	Richard Uhlig, David Nagle, Timothy J. Stanley, Trevor N. Mudge, Stuart Sechrest, Richard B. Brown	Design Tradeoffs for Software-Managed TLBs.	ACM Trans. Comput. Syst.	1994	DBLP DOI BibTeX RDF	translation lookaside buffer (TLB), trap-driven simulation, hardware monitoring
1	J. Bradley Chen, Anita Borg, Norman P. Jouppi	A Simulation Based Study of TLB Performance.	ISCA	1992	DBLP DOI BibTeX RDF