Search results for "Tadashi Yasufuku"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.	ISQED	2012	DBLP DOI BibTeX RDF
1	Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai	Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.	ISLPED	2011	DBLP BibTeX RDF
1	Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.	ISLPED	2011	DBLP BibTeX RDF
1	Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai	12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates.	DAC	2011	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.	ISLPED	2009	DBLP DOI BibTeX RDF	boost converter, inductor design, SSD, charge pump
1	Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories.	3DIC	2009	DBLP DOI BibTeX RDF

Publications of "Tadashi Yasufuku" ( http://dblp.L3S.de/Authors/Tadashi_Yasufuku )