Search results for "Tadayoshi Horita"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Tadayoshi Horita, Itsuo Takanami	An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications.	Transactions on Computational Science	2011	DBLP DOI BibTeX RDF
1	Tadayoshi Horita, Itsuo Takanami	An FPGA-based fast classifier with high generalization property.	SIGARCH Computer Architecture News	2010	DBLP DOI BibTeX RDF
1	Tadayoshi Horita, Itsuo Takanami	An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation.	PDPTA	2009	DBLP BibTeX RDF
1	Tadayoshi Horita, Koichi Kitano, Koji Teramoto	A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems.	PDPTA	2009	DBLP BibTeX RDF
1	Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami	Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.	PDPTA	2009	DBLP BibTeX RDF
1	Tadayoshi Horita, Yuuji Katou, Itsuo Takanami	An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Tadayoshi Horita, Itsuo Takanami, Masatoshi Mori	Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Tadayoshi Horita, Takurou Murata, Itsuo Takanami	A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.	DFT	2006	DBLP DOI BibTeX RDF	weight fault, neuron fault, fault tolerance, FPGA, VHDL, multilayer neural network
1	Tadayoshi Horita, Itsuo Takanami	Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.	PRDC	2001	DBLP DOI BibTeX RDF
1	Tadayoshi Horita, Itsuo Takanami	Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays
1	Tadayoshi Horita, Itsuo Takanami	A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.	PDPTA	2000	DBLP BibTeX RDF
1	Tadayoshi Horita, Itsuo Takanami	A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays.	ISPAN	2000	DBLP DOI BibTeX RDF	Hierarchical interconnection, Wafer scale integration (WSI), 3D stacked implementation, Peak number of vertical links, Interconnection networks, Massively parallel computer
1	Tadayoshi Horita, Itsuo Takanami	Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.	ISPAN	1999	DBLP DOI BibTeX RDF	The 1 1/2-track switch model, wefer scale integration, reconfiguration, yield enhancement, mesh-connected processor arrays
1	Itsuo Takanami, Tadayoshi Horita	Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays
1	Itsuo Takanami, Tadayoshi Horita	A built-in self-reconfigurable scheme for 3D mesh arrays.	ISPAN	1997	DBLP DOI BibTeX RDF	fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures
1	Tadayoshi Horita, Itsuo Takanami	A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.	ISPAN	1997	DBLP DOI BibTeX RDF	mesh arrays, the 1frac{1}{2} track-switch model, fault-tolerance, polynomial time algorithm, wafer scale integration

Publications of "Tadayoshi Horita" ( http://dblp.L3S.de/Authors/Tadayoshi_Horita )