| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kiyoung Kim, Taewhan Kim |
Algorithm for synthesizing design context-aware fast carry-skip adders.  |
ASP-DAC  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tak-Yung Kim, Taewhan Kim |
Clock Tree synthesis for TSV-based 3D IC designs. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hochang Jang, Deokjin Joo, Taewhan Kim |
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jongyoon Jung, Taewhan Kim |
Scheduling and Resource Binding Algorithm Considering Timing Variation. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim |
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Deokjin Joo, Taewhan Kim |
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoung-Hwan Lim, Taewhan Kim |
An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongho Lee, Taewhan Kim |
A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Taewhan Kim |
Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results. |
JCSE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin |
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | HaNeul Chon, Taewhan Kim |
Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC. |
Comput. J. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Minseok Kang, Taewhan Kim |
Clock buffer polarity assignment considering the effect of delay variations. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tak-Yung Kim, Taewhan Kim |
Clock tree synthesis with pre-bond testability for 3D stacked IC designs. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
optimization, routing, buffer insertion, 3D ICs, clock tree |
| 1 | Tak-Yung Kim, Taewhan Kim |
Clock tree embedding for 3D ICs. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongho Lee, Taewhan Kim |
Technique for controlling power-mode transition noise in distributed sleep transistor network. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tak-Yung Kim, Taewhan Kim |
Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew. |
Green Computing Conference |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim |
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | ByungHyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim |
Thermal sensor allocation and placement for reconfigurable systems. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
optimal placement, unate-covering problem, reconfigurable system, Thermal sensor |
| 1 | Pilok Lim, Ki-Seok Chung, Taewhan Kim |
Thermal-Aware High-Level Synthesis Based on Network Flow Method. |
Journal of Circuits, Systems, and Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim |
Interconnect and communication synthesis for distributed register-file microarchitecture. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Benjamin Carrión Schäfer, Taewhan Kim |
Autonomous temperature control technique in VLSI circuits through logic replication. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hochang Jang, Taewhan Kim |
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
clock synthesis, power/ground noise, buffer insertion |
| 1 | HaNeul Chon, Taewhan Kim |
Timing variation-aware task scheduling and binding for MPSoC. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jongyoon Jung, Taewhan Kim |
Timing variation-aware high-level synthesis considering accurate yield computation. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi |
Introduction to embedded systems week 2006 special issue. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Benjamin Carrión Schäfer, Taewhan Kim |
Hotspots Elimination and Temperature Flattening in VLSI Circuits. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin |
Power-gating-aware high-level synthesis. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | ByungHyun Lee, Taewhan Kim |
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim |
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yesin Ryu, Taewhan Kim |
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Taewhan Kim, Jungeun Kim |
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongseok Choi, Naehyuck Chang, Taewhan Kim |
DC-DC Converter-Aware Power Management for Low-Power Embedded Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim |
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro (eds.) |
Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007 |
CASES |
2007 |
DBLP BibTeX RDF |
|
| 1 | Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim |
Temperature-Aware Compilation for VLIWProcessors. |
RTCSA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhenmin Li, Taewhan Kim |
Address Code Optimization Exploiting Code Scheduling in DSP Applications. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jongyoon Jung, Taewhan Kim |
Timing variation-aware high-level synthesis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonseo Choi, Taewhan Kim |
Memory Access Driven Storage Assignment for Variables in Embedded System Design. |
Journal of Circuits, Systems, and Computers |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaewon Seo, Taewhan Kim, Joonwon Lee |
Optimal intratask dynamic voltage-scaling technique and its practical extensions. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Young-Jun Kim, Taewhan Kim |
A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. |
VLSI Signal Processing |
2006 |
DBLP DOI BibTeX RDF |
resource allocation/mapping, multi-mode/multi-task applications, HW/SW partitioning |
| 1 | Junhyung Um, Taewhan Kim |
Resource Sharing Combined with Layout Effects in High-Level Synthesis. |
VLSI Signal Processing |
2006 |
DBLP DOI BibTeX RDF |
resource allocation, high-level synthesis, layout |
| 1 | Young-Jun Kim, Taewhan Kim |
HW/SW partitioning techniques for multi-mode multi-task embedded applications. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
scheduling, allocation, co-design, binding |
| 1 | Seongsoo Hong, Wayne Wolf, Krisztián Flautner, Taewhan Kim (eds.) |
Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006 |
CASES |
2006 |
DBLP BibTeX RDF |
|
| 1 | Taewhan Kim |
Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. |
RTCSA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim |
A systematic IP and bus subsystem modeling for platform-based system design. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Pilok Lim, Taewhan Kim |
Thermal-aware high-level synthesis based on network flow method. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
power consumption, temperature, binding |
| 1 | Woo-Cheol Kwon, Taewhan Kim |
Optimal voltage allocation techniques for dynamically variable voltage processors. |
ACM Trans. Embedded Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
scheduling, low power design, Dynamic voltage scaling, variable voltage processor |
| 1 | Yoonseo Choi, Taewhan Kim, Hwansoo Han |
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongseok Choi, Naehyuck Chang, Taewhan Kim |
DC-DC converter-aware power management for battery-operated embedded systems. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
low power, voltage scaling, DC-DC converter |
| 1 | Jungeun Kim, Taewhan Kim |
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
scheduling, binding, memory access |
| 1 | Jaewon Seo, Taewhan Kim, Nikil D. Dutt |
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung |
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim |
Coupling-aware high-level interconnect synthesis [IC layout]. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Keoncheol Shin, Taewhan Kim |
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Keoncheol Shin, Taewhan Kim |
Leakage power minimization for the synthesis of parallel multiplier circuits. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
synthesis, power optimization |
| 1 | Chun-Gi Lyuh, Taewhan Kim |
Memory access scheduling and binding considering energy minimization in multi-bank memory systems. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
scheduling, binding, low energy design |
| 1 | Jaewon Seo, Taewhan Kim, Ki-Seok Chung |
Profile-based optimal intra-task voltage scheduling for hard real-time applications. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
intra-task voltage scheduling, DVS, low energy design |
| 1 | Yoonseo Choi, Taewhan Kim |
Memory access driven storage assignment for variables in embedded system design. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Keoncheol Shin, Taewhan Kim |
An integrated approach to timing-driven synthesis and placement of arithmetic circuits. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim |
Resource-constrained low-power bus encoding with crosstalk delay elimination. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang |
Minimum delay optimization for domino circuits - a coupling-aware approach. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
Logic synthesis, coupling, domino logic, delay minimization |
| 1 | Sungpack Hong, Taewhan Kim |
Bus Optimization for Low Power in High-Level Synthesis. |
Journal of Circuits, Systems, and Computers |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonseo Choi, Taewhan Kim |
Address assignment in DSP code generation - an integrated approach. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhyung Um, Taewhan Kim |
Synthesis of arithmetic circuits considering layout effects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang |
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda |
Memory allocation and mapping in high-level synthesis - an integrated approach. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Gi Lyuh, Taewhan Kim |
High-level synthesis for low power based on network flow method. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonseo Choi, Taewhan Kim |
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
page/burst modes, embedded system, memory layout, storage assignment |
| 1 | Woo-Cheol Kwon, Taewhan Kim |
Optimal voltage allocation techniques for dynamically variable voltage processors. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
scheduling, low power design, variable voltage processor |
| 1 | Junhyung Um, Taewhan Kim |
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu |
Logic transformation for low-power synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
logic transformation, power estimation model, low power, Logic synthesis |
| 1 | Yoonseo Choi, Taewhan Kim |
Binding Algorithm for Power Optimization Based on Network Flow Method. |
Journal of Circuits, Systems, and Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Seok Chung, Taewhan Kim, C. L. Liu |
A Complete Model for Glitch Analysis in Logic Circuits. |
Journal of Circuits, Systems, and Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang |
Domino logic synthesis based on implication graph. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu |
Synthesis and Optimization of Combinational Interface Circuits. |
VLSI Signal Processing |
2002 |
DBLP DOI BibTeX RDF |
embedded systems, logic circuit, interface synthesis |
| 1 | Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda |
An integrated algorithm for memory allocation and assignment in high-level synthesis. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
memory assignemt, scheduling effect, memory allocation, memory design |
| 1 | Yoonseo Choi, Taewhan Kim |
Address assignment combined with scheduling in DSP code generation. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
offset assignment, scheduling, code generation |
| 1 | Junhyung Um, Taewhan Kim |
Layout-aware synthesis of arithmetic circuits. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
layout, high performance, carry-save-adder |
| 1 | Jaewon Seo, Taewhan Kim |
Memory exploration utilizing scheduling effects in high-level synthesis. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonseo Choi, Taewhan Kim |
An efficient low-power binding algorithm in high-level synthesis. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Unni Narayanan, Ki-Seok Chung, Taewhan Kim |
Enhanced bus invert encodings for low-power. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonseo Choi, Taewhan Kim |
Address code optimization using code scheduling for digital signal processors. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim |
Coupling-aware high-level interconnect synthesis for low power. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhyung Um, Jae-hoon Kim, Taewhan Kim |
Layout-driven resource sharing in high-level synthesis. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhyung Um, Taewhan Kim |
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
VLSI, arithmetic circuits, Carry-save-addition |
| 1 | Ki-Seok Chung, Taewhan Kim, C. L. Liu |
G-vector: A New Model for Glitch Analysis in Logic Circuits. |
VLSI Signal Processing |
2001 |
DBLP DOI BibTeX RDF |
synthesis, power estimation, logic circuits, glitches |
| 1 | Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung |
An accurate evaluation of routing density for symmetrical FPGAs. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
VLSI/CAD algorithm, symmetrical FPGA, FPGA routing |
| 1 | Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu |
A Static Estimation Technique of Power Sensitivity in Logic Circuits. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngtae Kim, Taewhan Kim |
Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu |
An Integrated Data Path Optimization for Low Power Based on Network Flow Method. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung |
A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Youngtae Kim, Taewhan Kim |
An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders. |
Journal of Circuits, Systems, and Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung |
Decomposition of Bus-Invert Coding for Low-Power I/O. |
Journal of Circuits, Systems, and Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Taewhan Kim, Junhyung Um |
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu |
Behavioral-level partitioning for low power design in control-dominated application. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhyung Um, Taewhan Kim, C. L. Liu |
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Taewhan Kim, Junhyung Um |
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). |
ASP-DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungpack Hong, Taewhan Kim |
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Gernot Koch, Taewhan Kim, Reiner Genevriere |
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Junhyung Um, Taewhan Kim, C. L. Liu |
Optimal allocation of carry-save-adders in arithmetic optimization. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
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