Search results for "Tai-Chen Chen"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ta-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen	Micro-bump assignment for 3D ICs using order relation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Tai-Hung Li, Wan-Chun Chen, Xian-Ting Cai, Tai-Chen Chen	Escape routing of differential pairs considering length matching.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu	ILP-based inter-die routing for 3D ICs.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang	Predictive Formulae for OPC With Applications to Lithography-Friendly Routing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang	Predictive formulae for OPC with applications to lithography-friendly routing.	DAC	2008	DBLP DOI BibTeX RDF	routing, DFM, OPC, lithography, RET
1	Tai-Chen Chen, Yao-Wen Chang	Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang	Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin	A novel framework for multilevel full-chip gridless routing.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Tai-Chen Chen, Yao-Wen Chang	Multilevel full-chip gridless routing considering optical proximity correction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang	Timing modeling and optimization under the transmission line model.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang	Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model.	ICCD	2001	DBLP BibTeX RDF

Publications of "Tai-Chen Chen" ( http://dblp.L3S.de/Authors/Tai-Chen_Chen )