Search results for "Takayasu Sakurai"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai	A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and ${\rm V}_{\rm TH}$-Tuned Oscillator With Fixed Charge Programming.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.	ISQED	2012	DBLP DOI BibTeX RDF
1	Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai	Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya	A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Tadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai	Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai	0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Lechang Liu, Takayasu Sakurai, Makoto Takamiya	0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Katsuyuki Ikeuchi, Hideki Kusamitsu, Mutsuo Daito, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai	1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai	Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Lechang Liu, Takayasu Sakurai, Makoto Takamiya	A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Designing ultra-low voltage logic.	ISLPED	2011	DBLP BibTeX RDF
1	Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.	ISLPED	2011	DBLP BibTeX RDF
1	Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection.	ISLPED	2011	DBLP BibTeX RDF
1	Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.	ISLPED	2011	DBLP BibTeX RDF
1	Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai	12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano	0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.	CICC	2011	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates.	DAC	2011	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai	100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul	Beyond the horizon: The next 10x reduction in power - Challenges and solutions.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Lechang Liu, Zhiwei Zhou, Takayasu Sakurai, Makoto Takamiya	A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai	Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda	2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai	0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Naoki Masunaga, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision.	CICC	2010	DBLP DOI BibTeX RDF
1	Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai	Silicon 3D-integration technology and systems.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai	Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva Narendra	The semiconductor industry in 2025.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Gil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai	A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.	3DIC	2010	DBLP DOI BibTeX RDF
1	Koichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai	3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's.	3DIC	2010	DBLP DOI BibTeX RDF
1	Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai	Misleading energy and performance claims in sub/near threshold digital systems.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai	Design of large area electronics with organic transistors.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai	An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai	A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai	A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.	ISLPED	2009	DBLP DOI BibTeX RDF	boost converter, inductor design, SSD, charge pump
1	Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya	Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test.	CICC	2009	DBLP DOI BibTeX RDF
1	Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda	A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories.	3DIC	2009	DBLP DOI BibTeX RDF
1	Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai	A capacitive coupling interface with high sensitivity for wireless wafer testing.	3DIC	2009	DBLP DOI BibTeX RDF
1	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.	ISQED	2008	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Next-generation power-aware design.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai	Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda	Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai	An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai	A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Meeting with the forthcoming IC design.	SBCCI	2007	DBLP DOI BibTeX RDF	3D chip stack, large-area electronics, organic circuits, scaling issues, SiP
1	Takayasu Sakurai	Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future".	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai	Trends of On-Chip Interconnects in Deep Sub-Micron VLSI.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai	Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda	A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai	Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai	Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai	A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai	Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai	Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction.	Systems and Computers in Japan	2005	DBLP DOI BibTeX RDF
1	Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai	/spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications.	IEEE Transactions on Multimedia	2005	DBLP DOI BibTeX RDF
1	Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai	More than two orders of magnitude leakage current reduction in look-up table for FPGAs.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang	Reshaping EDA for power.	DAC	2003	DBLP DOI BibTeX RDF
1	Seongsoo Lee, Seungjun Lee, Takayasu Sakurai	Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems.	Journal of Circuits, Systems, and Computers	2002	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
1	Koichi Nose, Takayasu Sakurai	Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.	ISLPED	2002	DBLP DOI BibTeX RDF
1	Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai	CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Minimizing power across multiple technology and design levels.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai	Variable threshold CMOS (VTCMOS) in series connected circuits.	ISLPED	2001	DBLP DOI BibTeX RDF	body effect factor, degradation factor, series connected circuits, substrate bias, variable threshold voltage CMOS, velocity saturation
1	Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai	Design methodology and optimization strategy for dual-VTH scheme using commercially available tools.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Takayasu Sakurai	Estimation of power distribution in VLSI interconnects.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Takayasu Sakurai	Coupling-Driven Bus Design for Low-Power Application-Specific Systems.	DAC	2001	DBLP DOI BibTeX RDF
1	Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai	An LSI for VDD-hopping and MPEG4 system based on the chip.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Koichi Nose, Takayasu Sakurai	Analysis and future trend of short-circuit power.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control.	ISQED	2000	DBLP DOI BibTeX RDF	VDD, VTH, VLSI, Low-power, CMOS
1	Koichi Nose, Soo-Ik Chae, Takayasu Sakurai	Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	gate capacitance, low supply voltage, low-power design
1	Seongsoo Lee, Takayasu Sakurai	Run-time voltage hopping for low-power real-time systems.	DAC	2000	DBLP DOI BibTeX RDF
1	Seongsoo Lee, Takayasu Sakurai	Run-time power control scheme using software feedback loop for low-power real-time application.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Nguyen Minh Duc, Takayasu Sakurai	Compact yet high performance (CyHP) library for short time-to-market with new technologies.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Takayasu Sakurai	Design challenges for 0.1um and beyond: embedded tutorial.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Koichi Nose, Takayasu Sakurai	Optimization of VDD and VTH for low-power and high speed applications.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai	Power Optimization of Real-Time Embedded Systems on Variable Speed Processors.	ICCAD	2000	DBLP BibTeX RDF
1	Koichi Nose, Takayasu Sakurai	Integrated Current Sensing Device for Micro IDDQ Test.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Hiroshi Kawaguchi, Takayasu Sakurai	Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines.	ASP-DAC	1998	DBLP BibTeX RDF
1	Tadahiro Kuroda, Takayasu Sakurai	Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design.	VLSI Signal Processing	1996	DBLP DOI BibTeX RDF
1	Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai	Substrate noise influence on circuit performance in variable threshold-voltage scheme.	ISLPED	1996	DBLP DOI BibTeX RDF

Publications of "Takayasu Sakurai" ( http://dblp.L3S.de/Authors/Takayasu_Sakurai )