Search results for "Tarek M. Taha"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kenneth L. Rice, Tarek M. Taha, Khan M. Iftekharuddin, Keith Anderson, Teddy Salan	GPGPU acceleration of Cellular Simultaneous Recurrent Networks adapted for maze traversals.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Chris Yakopcic, Tarek M. Taha, Guru Subramanyam, Robinson E. Pino, Stanley Rogers	Analysis of a memristor based 1T1M crossbar architecture.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Chris Yakopcic, Tarek M. Taha, Guru Subramanyam, Stanley Rogers	Multiple memristor read and write circuit for neuromorphic applications.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Pavan Yalamanchili, Sumod K. Mohan, Rommel Jalasutram, Tarek M. Taha	Acceleration of hierarchical Bayesian network based cortical models on multicore architectures.	Parallel Computing	2010	DBLP DOI BibTeX RDF
1	Bing Han, Tarek M. Taha	Neuromorphic models on a GPGPU cluster.	IJCNN	2010	DBLP DOI BibTeX RDF
1	Chris Yakopcic, Eunsung Shin, Tarek M. Taha, Guru Subramanyam, P. Terrence Murray, Stanley Rogers	Fabrication and testing of memristive devices.	IJCNN	2010	DBLP DOI BibTeX RDF
1	Tarek M. Taha, Pavan Yalamanchili, Mohammad A. Bhuiyan, Rommel Jalasutram, Chong Chen, Richard Linderman	Neuromorphic algorithms on clusters of PlayStation 3s.	IJCNN	2010	DBLP DOI BibTeX RDF
1	Christopher N. Vutsinas, Tarek M. Taha, Kenneth L. Rice	A context switching streaming memory architecture to accelerate a neocortex model.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Kenneth L. Rice, Tarek M. Taha, Christopher N. Vutsinas	Scaling analysis of a neocortex inspired cognitive model on the Cray XD1.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF	Cognitive algorithms, Performance scaling, Parallel computing, Reconfigurable computing
1	Pavan Yalamanchili, Sumod K. Mohan, Tarek M. Taha	Implementing a hierarchical Bayesian visual cortex model on multi-core processors.	ACM Southeast Regional Conference	2009	DBLP DOI BibTeX RDF	performance, measurement, experimentation
1	Kenneth L. Rice, Mohammad A. Bhuiyan, Tarek M. Taha, Christopher N. Vutsinas, Melissa C. Smith	FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition.	ReConFig	2009	DBLP DOI BibTeX RDF	FPGA, spiking neural networks
1	Tarek M. Taha, Pavan Yalamanchili, Mohammad A. Bhuiyan, Rommel Jalasutram, Sumod K. Mohan	Parallelizing two classes of neuromorphic models on the Cell multicore architecture.	IJCNN	2009	DBLP DOI BibTeX RDF
1	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
1	Christopher N. Vutsinas, Tarek M. Taha, Kenneth L. Rice	A neocortex model implementation on reconfigurable logic with streaming memory.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Kenneth L. Rice, Christopher N. Vutsinas, Tarek M. Taha	A preliminary investigation of a neocortex model implementation on the Cray XD1.	SC	2007	DBLP DOI BibTeX RDF	cognitive algorithms, FPGA, reconfigurable, application performance
1	Clint W. Smullen, Tarek M. Taha	PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis.	WCAE	2006	DBLP DOI BibTeX RDF
1	Kiruthika Selvamani, Tarek M. Taha	Estimating critical region parallelism to guide platform retargeting.	ACM Southeast Regional Conference	2005	DBLP DOI BibTeX RDF	analytical model, performance prediction
1	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
1	Linda M. Wills, Tarek M. Taha, Lewis B. Baumstark Jr., D. Scott Wills	Estimating Potential Parallelism for Platform Retargeting. (PDF / PS)	WCRE	2002	DBLP DOI BibTeX RDF
1	Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl	Heterogeneous architecture models for interconnect-motivated system design.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl	Exploring Microprocessor Architectures for Gigascale Integration.	ARVLSI	1999	DBLP DOI BibTeX RDF	Billion Transistor, Future Tecnologies, Architecture, Microprocessors

Publications of "Tarek M. Taha" ( http://dblp.L3S.de/Authors/Tarek_M._Taha )