|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 6 occurrences of 6 keywords
|
|
|
|
|
Results
Found 25 publication records. Showing 25 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ritesh Ray Chaudhuri, Joydeep Basu, Tarun Kanti Bhattacharyya |
Design and Fabrication of Micromachined Resonators  |
CoRR  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Anindya Lal Roy, Anirban Bhattacharya, Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya |
Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Manas Kumar Hati, Tarun Kanti Bhattacharyya |
A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | R. Mukhiya, A. Bagolini, T. K. Bhattacharyya, L. Lorenzelli, M. Zen |
Experimental study and analysis of corner compensation structures for CMOS compatible bulk micromachining using 25 wt% TMAH. |
Microelectronics Journal |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Basu, Anirban Bhattacharya, Subha Chakraborty, T. K. Bhattacharyya |
A Comparative Study Between a Micromechanical Cantilever Resonator and MEMS-based Passives for Band-pass Filtering Application |
CoRR |
2011 |
DBLP BibTeX RDF |
|
| 1 | A. Perumal, T. K. Bhattacharyya |
Design of 1 V CMOS VCO followed by proposed source degeneration based CML flip-flops for 2.4 GHz short range wireless applications. |
ICWET |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Subha Chakraborty, T. K. Bhattacharyya |
Development of a Micro-mechanical Logic Inverter for Low Frequency MEMS Sensor Interfacing. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anupam Dutta, T. K. Bhattacharyya |
Low Offset, Low Noise, Variable Gain Interfacing Circuit with a Novel Scheme for Sensor Sensitivity and Offset Compensation for MEMS Based, Wheatstone Bridge Type, Resistive Smart Sensor. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Manas Kumar Hati, Tarun Kanti Bhattacharyya |
Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sambit Datta, Ashudeb Dutta, Kunal Datta, Tarun Kanti Bhattacharyya |
Pseudo Concurrent Quad-Band LNA Operating in 900 MHz/1.8 GHz and 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhisek Dey, Tarun Kanti Bhattacharyya |
Low power 120 KSPS 12bit SAR ADC with a novel switch control method for internal CDAC. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao, Eric A. M. Klumperink |
Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit |
| 1 | Ramen Dutta, T. K. Bhattacharyya |
A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Debashis Mandal, T. K. Bhattacharyya |
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design. |
JCP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | T. K. Bhattacharyya, Anandaroop Ghosh |
Behavioral Modeling of a CMOS Compatible High Precision MEMS Based Electron Tunneling Accelerometer. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amal Kumar Kundu, Subho Chatterjee, Tarun Kanti Bhattacharyya |
A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amal Kumar Kundu, I. Kharagpur, Tathagato Rai Dastidar, Tarun Kanti Bhattacharyya, Partha Ray |
A methodology for efficient design of analog circuits using an automated simulation based synthesis tool. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashudeb Dutta, Kaushik Dasgupta, T. K. Bhattacharyya |
Compact small signal modeling and PSO-based input matching of a packaged CMOS LNA in subthreshold region. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Debashis Mandal, T. K. Bhattacharyya |
7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Goshaidas Ray, Sitansu Dey, T. K. Bhattacharyya |
Reaching condition for variable-structure output feedback controller using a search technique. |
Int. J. Systems Science |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | T. K. Bhattacharyya, Shreyas Sen, Debashis Mandal, S. K. Lahiri |
Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabir K. Saha, Ashudeb Dutta, A. Patra, T. K. Bhattacharyya |
Design of a 1 V Low Power 900 MHz QVCO. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya |
A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18ยต Digital CMOS. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta |
Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
CMOS RF, ZigBee, Phase locked loop, Analog integrated circuits, Frequency synthesizer |
| 1 | Amlan Ghosh, Bevin G. Perumana, Ashudeb Dutta, Padmanava Sen, Yogesh Kumar, Vipul Garg, T. K. Bhattacharyya, Nirmal B. Chakrabarti |
Design and Implementation of 935 MHz FM Transceiver for Radio Telemetry and 2.45 GHz Direct AQPSK Transmitter in CMOS. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #25 of 25 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")