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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 7 keywords
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Results
Found 25 publication records. Showing 25 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Terrence S. T. Mak |
Truncation error analysis of MTBF computation for multi-latch synchronizers.  |
Microelectronics Journal  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev |
Power adaptive computing system design in energy harvesting environment. |
ICSAMOS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon |
On-chip dynamic programming networks using 3D-TSV integration. |
ICSAMOS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yu Zhou, Terrence S. T. Mak, Alex Yakovlev |
Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems. |
ACSD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Nizar Dahir, Terrence S. T. Mak, Alex Yakovlev |
Communication centric on-chip power grid models for networks-on-chip. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon |
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon |
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yu Li, Terrence S. T. Mak, Alex Yakovlev |
Redressing timing issues for speed-independent circuits in deep submicron age. |
DATE |
2011 |
DBLP BibTeX RDF |
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| 1 | Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, M. Palesi |
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon |
A CMOS Current-Mode Dynamic Programming Circuit. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Wave-pipelined intra-chip signaling for on-FPGA communications. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon |
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. |
FPL |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung |
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A DP-network for optimal dynamic routing in network-on-chip. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
optimal and sub-optimal routing, dynamic programming, network-on-chip, adaptive routing |
| 1 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Implementation of Wave-Pipelined Interconnects in FPGAs. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Interconnection lengths and delays estimation for communication links in FPGAs. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
communciation link, interconnection length prediction, FPGA |
| 1 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Global interconnections in FPGAs: modeling and performance analysis. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
FPGA, throughput, interconnection, wave-pipelined |
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
High-throughput interconnect wave-pipelining for global communication in FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon |
A Current-Mode Analog Circuit for Reinforcement Learning Problems. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
On-FPGA Communication Architectures and Design Factors. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Terrence S. T. Mak, Kai-Pui Lam |
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Terrence S. T. Mak, Kai-Pui Lam |
On Computing Maximum Likelihood Phylogeny Using FPGA p. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, Kai-Pui Lam |
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. |
CSB |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Terrence S. T. Mak, Kai-Pui Lam |
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. |
CSB |
2003 |
DBLP DOI BibTeX RDF |
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