Search results for "Test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Nancy S. Eickelmann, Debra J. Richardson	An Evaluation of Software Test Environment Architectures.	ICSE	1996	DBLP BibTeX RDF	CITE, CONVEX Integrated Test Environment, PROLOG Test Environment, Version II, PROTest II, Software Architectural Analysis Method, TAOS, Testing with Analysis and Oracle Support, architecturally imposed constraints, environment functions allocation, implementation structures, processing algorithms, software test environment architectures, test development, test failure analysis, test measurement, test process automation, performance, software architecture, programming environments, program testing, software reusability, extensibility, reusability, software performance evaluation, portability, functionality, computer aided software engineering, software portability, testing tools, data representation, reference architecture, modifiability, test management, modifications, test planning, test execution, SAAM
11	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
10	Naina Mittal, Ira Acharya	An Open Framework for Managed Regression Testing.	TestCom	2003	DBLP DOI BibTeX RDF	managed testing, networking equipment, test bench, hierarchical test case management, test plan tree, framework deployment, test-cycle reduction, testing tool collaboration, regression testing, black-box testing, Test automation, test framework, test planning, test execution, test scripts
10	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
10	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
10	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
10	T. Haulin	Built-in parametric test for controlled impedance I/Os.	VTS	1997	DBLP DOI BibTeX RDF	controlled impedance I/Os, built-in parametric test, full DC parametrics, full speed AC tests, lower cost ATE, differential signal I/Os, single-ended signal I/Os, short circuit proof drivers, B9 test method, bidirectional I/O, differential receivers, differential transmitters, diagnostic tests, narrow pulse test, contact test, high speed test logic, built-in self test, functional test, boundary scan, static tests
10	M. Miegler, Werner Wolz	Development of test programs in a virtual test environment.	VTS	1996	DBLP DOI BibTeX RDF	test programs development, virtual test environment, quality-assured mixed-signal test programs, standard test description language, VTML, Virtual Test Modelling Language, standardized description models, test system resources, equivalent simulation models, VLSI, integrated circuit testing, design for testability, integrated circuit design, circuit CAD, automatic test software
10	Hiroshi Date, Michinobu Nakao, Kazumi Hatayama	A parallel sequential test generation system DESCARTES based on real-valued logic simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	parallel sequential test generation system, DESCARTES, real-valued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuck-at faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality
9	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
9	Kuen-Jong Lee, Cheng-I. Huang	A hierarchical test control architecture for core based design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
9	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
9	Albrecht P. Stroele, Frank Mayer	Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	loop folding, test configuration, test register, built-in self-test, test schedule, test application time, Accumulator
9	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
9	Susana Stoica	A lifecycle approach to design validation is it necessary? Is it feasible?	ITC	1998	DBLP DOI BibTeX RDF	Lifecycle test, system approach to design and test, Robust Test Methodology (RTM), Design Validation (DV), software /hardware test methods, requirements specifications test, QA-type testing, Test Plan (TP) boilerplate, test optimization considering full lifecycle DV, black box testing, white box testing
9	Albrecht P. Stroele, Frank Mayer	Methods to reduce test application time for accumulator-based self-test.	VTS	1997	DBLP DOI BibTeX RDF	accumulator-based self-test, test length minimization, simulation-based reseeding method, random pattern testable circuits, reverse order simulation, hard fault detection, optimal input value, test length reductions, data path blocks, BIST scheme, ATALANTA fault simulation, combinatorial circuit testing, built-in self test, fault coverage, embedded processor, test pattern generators, circuit optimization, test application time reduction, forward simulation
9	Fidel Muradali, Janusz Rajski	A self-driven test structure for pseudorandom testing of non-scan sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
9	S. Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
8	Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee	Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	wafer probe test, test yield, loopback test, DFT, RF test, low-cost test
8	Hong Zhu, Joseph Robert Horgan, S. C. Cheung, J. Jenny Li	The first international workshop on automation of software test.	ICSE	2006	DBLP DOI BibTeX RDF	component integration test, test adequacy and coverage, test cost and effectiveness, test tools and environments, software test, model-based test, test case generation, software automation
8	Achintya Halder, Soumendu Bhattacharya, Ganesh Srinivasan, Abhijit Chatterjee	A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode.	VLSI Design	2005	DBLP DOI BibTeX RDF	System-level test, Loop-back test, wireless transceiver test, Analog and mixed-signal test, RF test, Specification test
8	Jochen Rivoir	Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	low-cost ATE, multi-site test, mixed-signal test, concurrent test, low-cost test, test resource partitioning
8	Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara	A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	test plan grouping, test controllers, partly compacted test plan tables, RTL data paths, test length
8	Erik Larsson, Zebo Peng	An Integrated Framework for the Design and Optimization of SOC Test Solutions.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	test access mechanism design, test resource placement, test conflicts, power consumption, test scheduling, SOC test, test resource partitioning
8	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
8	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
8	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
8	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast hierarchical test path construction for DFT-free controller-datapath circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
8	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
8	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
8	Michel Renovell, Joan Figueras, Yervant Zorian	Test of RAM-based FPGA: methodology and application to the interconnect.	VTS	1997	DBLP DOI BibTeX RDF	RAM-based FPGA, manufacturing test procedure, user test procedure, orthogonal test configuration, diagonal-1 test configuration, diagonal-2 test configuration, field programmable gate arrays, interconnect
8	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
8	Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting	Syndrome Simulation And Syndrome Test For Unscanned Interconnects.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	unscanned interconnects, syndrome test methodology, event driven syndrome simulation, boundary scan environment, faulty syndromes, fault-free syndromes, tolerable error rate, partially scanned PCB, board level testing, test pattern generation, boundary scan testing, test length, MCM, set covering problem, simulation algorithm, weighted random patterns, test cost reduction
8	Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis	An efficient comparative concurrent Built-In Self-Test technique.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
8	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
7	Qizhang Yin, William R. Eisenstadt, Tian Xia	Wireless System for Microwave Test Signal Generation.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	wireless test, RF IC, RF BIST, LNA test, microwave test, embedded test
7	Joonsung Park, Hongjoong Shin, Jacob A. Abraham	Parallel Loopback Test of Mixed-Signal Circuits.	VTS	2008	DBLP DOI BibTeX RDF	Test Quality and Reliability, Loopback Test, Characterization, Mixed-signal Test, Parallel Test
7	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.	European Test Symposium	2007	DBLP DOI BibTeX RDF	Dynamically reconfigurable processors, optimal contexts, test frames, self-test, test application time
7	Kalpesh Zinjuwadia, Perry Alexander	DVTG and Test Harnessing using Rosetta Specifications.	ECBS	2004	DBLP DOI BibTeX RDF	Rosetta, DVTG, Test Initialization, Test Harnessing, XML, Test Vectors, Test Requirements, Test Scenarios
7	Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara	A DFT Selection Method for Reducing Test Application Time of System-on-Chips.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	wrapper, design for test, test scheduling, test access mechanism
7	Makoto Sugihara, Hiroto Yasuura	Optimization of Test Accesses with a Combined BIST and External Test Scheme.	VLSI Design	2002	DBLP DOI BibTeX RDF	external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
7	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
7	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Compaction-based test generation using state and fault information.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
7	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A built-in self-test and self-diagnosis scheme for embedded SRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-diagnosis scheme, fault diagnosis, fault diagnosis, built-in self test, built-in self-test, system-on-chip, memory test, SRAM chips, embedded SRAM
7	Emil Gizdarski, Hideo Fujiwara	Spirit: satisfiability problem implementation for redundancy identification and test generation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
7	Sying-Jyan Wang, Chen-Jung Wei	Efficient built-in self-test algorithm for memory.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
7	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
7	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
7	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
7	Chen-Huan Chiang, Sandeep K. Gupta	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
7	Ahmed Khoumsi	A new method for testing real time systems.	RTCSA	2000	DBLP DOI BibTeX RDF	real-time systems testing, test sequence executability, test sequence execution, real-time systems, constraints, automatic test pattern generation, program testing, timed automata, conformance testing, conformance testing, sequences, test case generation, automata theory, state explosion, test architecture, test sequence generation, continuous-time systems
7	Abhijit Jas, Kartik Mohanram, Nur A. Touba	An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Weighted Pseudo-Random Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
7	Thomas J. Ostrand, Aaron Anodide, Herbert Foster, Tarak Goradia	A Visual Test Development Environment for GUI Systems.	ISSTA	1998	DBLP DOI BibTeX RDF	GUI-based system, capture/reply, test maintenance, visual editor, testing, test generation, test coverage, test designer, test scenario
7	Yuejian Wu, Sanjay Gupta	Built-In Self-Test for Multi-Port RAMs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST)
7	Irith Pomeranz, Sudhakar M. Reddy	On the Compaction of Test Sets Produced by Genetic Optimization.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test generation, test compaction, genetic optimization, n-detection test sets
7	Jonathan T.-Y. Chang, Edward J. McCluskey	SHOrt voltage elevation (SHOVE) test for weak CMOS ICs.	VTS	1997	DBLP DOI BibTeX RDF	short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC
7	Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada	A practical approach to instruction-based test generation for functional modules of VLSI processors.	VTS	1997	DBLP DOI BibTeX RDF	VLSI processors, instruction-based test generation, functional test pattern generation, gate level faults, constrained test generation, ALU oriented test pattern generation system, VLSI, functional modules, ALPS
7	Irith Pomeranz, Sudhakar M. Reddy	On improving genetic optimization based test generation.	ED&TC	1997	DBLP DOI BibTeX RDF	propagation Citation: I. Pomeranz, S.M. Reddy, On improving genetic optimization based test generation, edtc, pp.506, 1997 European Design and Test Conference (ED&TC '97), 1997 Peer Review Notice, Give Us Feedback Usage of this product signifies your acceptance of the Terms of Use. var addtoMethod=1, var AddURL = escape(http://doi.ieeecomputersociety.org/), var AddTitle = escape(On improving genetic optimization based test generation), Open Download Liferay.Portlet.onLoad({ canEditTitle: false, columnPos: 1, isStatic: 'end', namespacedId: 'p_p_id_digitallibraryabstract_WAR_plugins_INSTANCE_DjbO_', portletId: 'digitallibraryabstract_WAR_plugins_INSTANCE_DjbO' }), genetic algorithms, test generation, fault coverage, activation, benchmark circuit, crossover operator, genetic optimization
7	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
7	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
7	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
7	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo	An Efficient PRPG Strategy By Utilizing Essential Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	PRPG, essential fault, multiple polynomial, Gauss elimination, pseudorandom test pattern, multivariable linear equation, deterministic test set, random pattern resistant circuit, don't care value, intelligent heuristic, ISCAS-85 benchmark, ISCAS-89 benchmark, built-in self test, BIST, fault coverage, LFSR, test length, hardware overhead, multiple seed
7	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
7	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
7	Michel Renovell, Florence Azaïs, Yves Bertrand	A design-for-test technique for multistage analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing
7	Irith Pomeranz, Sudhakar M. Reddy	Static compaction for two-pattern test sets.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults
7	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, transformation, timing, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
7	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
7	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
7	Joan Carletta, Christos A. Papachristou	Structural constraints for circular self-test paths.	VTS	1995	DBLP DOI BibTeX RDF	circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits
7	Lahouari Sebaa, Norm Gardner, Robert Neidorff, Rich Valley	Self-test in a VCM driver chip.	VTS	1995	DBLP DOI BibTeX RDF	driver circuits, bridge circuits, digital-analogue conversion, pulse amplifiers, VCM driver chip, self-test mode, complex mixed-signal device, device under test, voice-coil motor, H-bridge amplifier, onchip D/A converter, self-test circuitry, 11 bit, built-in self test, integrated circuit testing, design for testability, mixed analogue-digital integrated circuits, instrumentation amplifiers
7	M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
7	Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self test for high-level synthesis.	VTS	1995	DBLP DOI BibTeX RDF	arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
7	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
6	Dongsoo Lee, Kaushik Roy	Viterbi-Based Efficient Test Data Compression.	European Test Symposium	2011	DBLP DOI BibTeX RDF	On-Chip Decompressor, Scalability, Logic Test, Test Data Compression, Low-Power Test
6	Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer	Reduced ATE Interface for High Test Data Compression.	European Test Symposium	2011	DBLP DOI BibTeX RDF	channel bandwidth management, embedded deterministic test, test interface, tri-modal compression, test data compression, scan-based designs
6	Feng Yuan, Xiao Liu, Qiang Xu	On High-Quality Test Pattern Selection and Manipulation.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Pseudo-functional testing, test overkill, test escape, test pattern selection
6	Milos Gligoric, Tihomir Gvero, Vilas Jagannath, Sarfraz Khurshid, Viktor Kuncak, Darko Marinov	Test generation through programming in UDITA.	ICSE	2010	DBLP DOI BibTeX RDF	Pex, UDITA, test filtering, test predicates, test generation, automated testing, test programs, Java PathFinder
6	Scott Davidson, Nur A. Touba	Guest Editors' Introduction: Progress in Test Compression.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	tester memory, don't-care bits, X values, test compression, test vectors, test data volume
6	Vladimir A. Zivkovic, Frank van der Heyden, Guido Gronthoud, Frans de Jong	Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design.	European Test Symposium	2008	DBLP DOI BibTeX RDF	Modular Test, Analog Test, Test Architecture
6	Sounil Biswas, R. D. (Shawn) Blanton	Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.	VTS	2008	DBLP DOI BibTeX RDF	pass-fail test data, boolean minimization, minimum constrained subset cover, Mixed-signal test, test compaction
6	Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li	A Case Study on At-Speed Testing for a Gigahertz Microprocessor.	DELTA	2008	DBLP DOI BibTeX RDF	test power consumption, test coverage, at-speed testing, test time, test data volume
6	Harry M. Sneed	Bridging the Concept to Implementation Gap in Software System Testing.	QSIC	2008	DBLP DOI BibTeX RDF	System test process, test cases, test design, test specification, test scripts
6	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
6	Guangyu Huang, Cher Ming Tan	Reverse Breakdown Voltage Measurement for Power P+NN+ Rectifier.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Forced voltage test, Forced current test, PIV test, Minimum required test time, Destruction during test
6	J. M. Gilbert, Ian M. Bell	The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	test escapes, test capability, electronics design, quality, test coverage, design for test, process capability
6	Anne Gattiker	Guest Editor's Introduction: Getting More Out of Test.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	electronic test, designers, debugging, diagnosis, International Test Conference, ITC, test engineers
6	Jun Zhou, Hans-Joachim Wunderlich	Software-based self-test of processors under power constraints.	DATE	2006	DBLP DOI BibTeX RDF	test program generation, low power test, processor test
6	Soumendu Bhattacharya, Abhijit Chatterjee	Optimized wafer-probe and assembled package test design for analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Assembled package, co-optimization, test cost minimization, test generation and co-optimization, wafer-probe, simulation, test, prototype, analog and mixed-signal test
6	Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya	Efficient Test Compaction for Pseudo-Random Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	built-in testing, test-data compression, Test compaction, pseudo-random testing
6	Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara	An Effective Design for Hierarchical Test Generation Based on Strong Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	Hierarchical test generation, strong testability, datapath, test plan
6	Sameer Goel, Rubin A. Parekhji	Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	delay fault simulation, N-detect coverage metrics, Delay fault test, test optimizations
6	Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel	Implementing a Scheme for External Deterministic Self-Test.	VTS	2005	DBLP DOI BibTeX RDF	Deterministic self-test, external BIST, test data compression, test resource partitioning
6	Robert C. Aitken	ITC is Cool.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	high-frequency test, board and system test, test compression, silicon debug, International Test Conference, ITC
6		Conference Reports.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	ETS 05, European Test Workshop, Eastern Europe, NATW 05, outlier screening, analog test, TTTC, embedded test, defect-based test, yield management
6	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	Reusing an on-chip network for the test of core-based systems.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	TAM and wrapper design, test reuse, network-on-chip, test scheduling, SoC test, Core-based test
6	Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa	Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction
6	Chih-Pin Su, Cheng-Wen Wu	A Graph-Based Approach to Power-Constrained SOC Test Scheduling.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	test integration, test scheduling, test access mechanism (TAM), SOC testing, test power, system-on-chip (SOC)
6	Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	Reducing test time with processor reuse in network-on-chip based systems.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test
6	Anshuman Chandra, Krishnendu Chakrabarty	Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	decompression architecture, precomputed test sets, test set encoding, system-on-a-chip test, variable-to-variable-length codes, Automatic test equipment (ATE), embedded core testing