Search results for "Timing optimization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
3	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
3	Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou	Incremental physical resynthesis for timing optimization.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, placement, logic synthesis, timing optimization
3	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
2	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
2	Val Pevzner, Andrew A. Kennings, Andy Fox	Physical optimization for FPGAs using post-placement topology rewriting.	ISPD	2009	DBLP DOI BibTeX RDF	fpga, timing optimization, physical synthesis
2	Virginia P. Sisiopiku, Abhishek Acharya, Michael Anderson, Daniel Turner	Evaluation of traffic signal performance under oversaturated conditions using VISTA.	SpringSim	2009	DBLP DOI BibTeX RDF	oversaturated arterials, signal timing optimization, traffic simulation
2	Hao Li, Yue Zhuo	Criticality history guided FPGA placement algorithm for timing optimization.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	fpga, placement, timing optimization
2	Ke Cao, Jiang Hu, Mosong Cheng	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Kumar Yelamarthi, Chien-In Henry Chen	Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
2	Jürgen Werber, Dieter Rautenbach, Christian Szegedy	Timing optimization by restructuring long combinatorial paths.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang	ECO timing optimization using spare cells.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Shih-Hsu Huang, Yow-Tyng Nieh	Clock skew scheduling with race conditions considered.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Sequential circuits, logic synthesis, performance optimization, timing optimization
2	Jiyoun Kim, Marios C. Papaefthymiou, José Neves	Parallelizing post-placement timing optimization.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Di Wu, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
2	Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura	Timing optimization by replacing flip-flops to latches.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Dazhi Sun, Rahim F. Benekohal, S. Travis Waller	Multi-objective Traffic Signal Timing Optimization Using Non-dominated Sorting Genetic Algorithm II.	GECCO	2003	DBLP DOI BibTeX RDF
2	Giancarlo Beraudo, John Lillis	Timing optimization of FPGA placements by logic replication.	DAC	2003	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
2	Wonjoon Choi, Kia Bazargan	Incremental Placement for Timing Optimization.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Supratik Chakraborty, Rajeev Murgai	Layout-Driven Timing Optimization by Generalized De Morgan Transform.	VLSI Design	2002	DBLP DOI BibTeX RDF	layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure
2	Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Timing optimization on routed designs with incremental placementand routing characterization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
2	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III	Integrated parametric timing optimization of digital systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
2	Abhijit Das	On the Transistor Sizing Problem.	VLSI Design	2000	DBLP DOI BibTeX RDF	Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint
2	John Lillis, Chung-Kuan Cheng	Timing optimization for multisource nets: characterization andoptimal repeater insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Chun-hong Chen, Chi-Ying Tsui	Timing Optimization of Logic Network Using Gate Duplication.	ASP-DAC	1999	DBLP DOI BibTeX RDF
2	Alexander Saldanha	Functional timing optimization.	ICCAD	1999	DBLP BibTeX RDF
2	Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita	Speeding up technology-independent timing optimization by network partitioning.	ICCAD	1997	DBLP DOI BibTeX RDF
2	Chen-Liang Fang, Wen-Ben Jone	Timing optimization by gate resizing and critical path identification.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Wing Ning Li	An efficient algorithm for computing a minimum node cutset from a vertex-disjoint path set for timing optimization.	SAC	1995	DBLP DOI BibTeX RDF	vertex-disjoint path, algorithm, graph, synthesis, timing optimization, maximum flow, cutset
2	Karen A. Bartlett, Gaetano Borriello, Sitaram Raju	Timing optimization of multiphase sequential logic.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
2	Kuang-Chien Chen, Saburo Muroga	Timing Optimization for Multi-Level Combinational Networks.	DAC	1990	DBLP DOI BibTeX RDF
1	Jiajia He, Zai-en Hou	Ant colony algorithm for traffic signal timing optimization.	Advances in Engineering Software	2012	DBLP DOI BibTeX RDF
1	Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang	Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu	ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li	Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yit Kwong Chin, K. C. Yong, Nurmin Bolong, S. S. Yang, Kenneth Tze Kin Teo	Multiple intersections traffic signal timing optimization with genetic algorithm.	ICCSCE	2011	DBLP DOI BibTeX RDF
1	Yi-Rong Chen, Hung-Ming Chen, Shih-Ying Liu	TSV-based 3D-IC placement for timing optimization.	SoCC	2011	DBLP DOI BibTeX RDF
1	Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang	ECO Timing Optimization Using Spare Cells and Technology Remapping.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Ximin Liu, Shoufeng Lu, Shiqiang Dai	A Macroscopic Timing Optimization Model for Signalized Intersections Based on an Extended Internal State Node Model.	CETS	2010	DBLP DOI BibTeX RDF
1	Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta	Accelerating Synchronous Sequential Circuits Using an Adaptive Clock.	VLSI Design	2010	DBLP DOI BibTeX RDF	VLSI, CAD, delays, Timing, sequential circuits, Timing optimization
1	Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Ying Zhou	Ultra-fast interconnect driven cell cloning for minimizing critical path delay.	ISPD	2010	DBLP DOI BibTeX RDF	gate duplication, physical synthesis, timing-driven placement
1	Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng	At-Speed Scan Test Method for the Timing Optimization and Calibration.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Mihir R. Choudhury, Kartik Mohanram	Timing-driven optimization using lookahead logic circuits.	DAC	2009	DBLP DOI BibTeX RDF	logic synthesis, timing optimization, lookahead
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Timing-driven N-way decomposition.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	logic design, decomposition, timing optimization
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.	NanoNet	2009	DBLP DOI BibTeX RDF	timing optimization, on-chip interconnect, repeater insertion, 3-D ICs
1	Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang	New spare cell design for IR drop minimization in Engineering Change Order.	DAC	2009	DBLP DOI BibTeX RDF	spare cell, IR drop, decoupling capacitor, ECO
1	Qingfeng Zhuge, Chun Jason Xue, Meikang Qiu, Jingtong Hu, Edwin Hsing-Mean Sha	Timing optimization via nest-loop pipelining considering code size.	Microprocessors and Microsystems - Embedded Hardware Design	2008	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.	JCP	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Sean X. Shi, David Z. Pan	Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Yifang Liu, Rupesh S. Shelar, Jiang Hu	Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Hosung (Leo) Kim, John Lillis	A framework for layout-level logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF	logic resynthesis, timing optimization
1	Yifang Liu, Jiang Hu, Weiping Shi	Multi-scenario buffer insertion in multi-core processor designs.	ISPD	2008	DBLP DOI BibTeX RDF	multi-core design, buffer insertion
1	Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah	Incremental Criticality and Yield Gradients.	DATE	2008	DBLP DOI BibTeX RDF
1	Yifang Liu, Jiang Hu, Weiping Shi	Buffering Interconnect for Multicore Processor Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien	Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Kai Zhu	Post-route LUT output polarity selection for timing optimization.	FPGA	2007	DBLP DOI BibTeX RDF	optimization, timing, polarity, FPGA lookup table
1	Yuanlin Lu, Vishwani D. Agrawal	Statistical Leakage and Timing Optimization for Submicron Process Variation.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Salim Chowdhury, John Lillis	Repeater insertion for concurrent setup and hold time violations with power-delay trade-off.	ISPD	2007	DBLP DOI BibTeX RDF	early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion
1	Vishal Khandelwal, Ankur Srivastava	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.	ISPD	2007	DBLP DOI BibTeX RDF	post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
1	Ruiming Chen, Hai Zhou	Fast Buffer Insertion for Yield Optimization Under Process Variations.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Shuo Yao, Michel Pasquier, Chai Quek	A foreign exchange portfolio management mechanism based on fuzzy neural networks.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
1	Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Juan Chen, Lihong Xu	Road-Junction Traffic Signal Timing Optimization by an adaptive Particle Swarm Algorithm.	ICARCV	2006	DBLP DOI BibTeX RDF
1	Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson	DDR2 DRAM Output Timing Optimization.	MTDT	2006	DBLP DOI BibTeX RDF
1	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	Voltage island aware floorplanning for power and timing optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu	Register binding for clock period minimization.	DAC	2006	DBLP DOI BibTeX RDF	high-level synthesis, clock skew, timing optimization
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Dominator-based partitioning for delay optimization.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	logic design, timing optimization, logic partitioning
1	Hosung (Leo) Kim, John Lillis, Milos Hrkic	Techniques for improved placement-coupled logic replication.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
1	Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri	Wire density driven global routing for CMP variation and timing.	ICCAD	2006	DBLP DOI BibTeX RDF	performance, VLSI, manufacturability, global routing
1	Bo Hu	Timing-driven placement for heterogeneous field programmable gate array.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Ilsoo Yun, Byungkyu Brian Park	Application of stochastic optimization method for an urban corridor.	Winter Simulation Conference	2006	DBLP DOI BibTeX RDF
1	Gang Chen, Jason Cong	Simultaneous placement with clustering and duplication.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	clustering, FPGA, Placement, legalization, duplication, redundancy removal
1	Shih-Hsu Huang, Yow-Tyng Nieh	Synthesis of nonzero clock skew circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Debjit Sinha, Narendra V. Shenoy, Hai Zhou	Statistical Timing Yield Optimization by Gate Sizing.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Chaojun Dong, Zhiyong Liu, Zulian Qiu	Urban Traffic Signal Timing Optimization Based on Multi-layer Chaos Neural Networks Involving Feedback.	ICNC	2005	DBLP DOI BibTeX RDF
1	Rajeev Murgai	Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	C. Santos, D. Ferrao, R. Reis, J. L. Guntzel	Incremental timing optimization for automatic layout generation.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jiyoun Kim, José Neves, Marios C. Papaefthymiou	Multi-Session Partitioning for Parallel Timing Optimization.	PDCAT	2005	DBLP DOI BibTeX RDF
1	Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi	Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations.	ICCAD	2005	DBLP BibTeX RDF
1	Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu	Race-condition-aware clock skew scheduling.	DAC	2005	DBLP DOI BibTeX RDF	sequential circuits, high performance, timing optimization
1	Yuzheng Ding, Peter Suaris, Nan-Chi Chou	The effect of post-layout pin permutation on timing.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, placement, logic synthesis, timing optimization
1	Timothy W. O'Neil, Edwin Hsing-Mean Sha	Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	scheduling, graph transformation, retiming, unfolding, data-flow graphs, timing optimization
1	Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin	How accurately can we model timing in a placement engine?	DAC	2005	DBLP DOI BibTeX RDF	differential timing analysis, linear programming, static timing analysis, timing-driven placement
1	Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers	High Level Synthesis of Timed Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Jingyu Xu, Xianlong Hong, Tong Jing	Timing-driven global routing with efficient buffer insertion.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester	Switch-factor based loop RLC modeling for efficient timing analysis.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Timing Optimization of Nested Loops Considering Code Size for DSP Applications.	ICPP	2004	DBLP DOI BibTeX RDF
1	Ryan Fung, Vaughn Betz, William Chow	Simultaneous short-path and long-path timing optimization for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Milos Hrkic, John Lillis, Giancarlo Beraudo	An approach to placement-coupled logic replication.	DAC	2004	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
1	Jia Wang, Hai Zhou	Minimal period retiming under process variations.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	process variations, retiming, statistical timing analysis
1	Xianlong Hong, Tong Jing, Jingyu Xu, Haiyun Bao, Jun Gu	CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing.	J. Comput. Sci. Technol.	2003	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu	An integrated floorplanning with an efficient buffer planning algorithm.	ISPD	2003	DBLP DOI BibTeX RDF	floorplanning, buffer insertion, routability
1	Andrew B. Kahng, Bao Liu	Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Bill Halpin, Naresh Sehgal, C. Y. Roger Chen	Detailed Placement with Net Length Constraints.	IWSOC	2003	DBLP DOI BibTeX RDF
1	Jordi Cortadella	Timing-driven logic bi-decomposition.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Stefanus Mantik, Igor L. Markov	Min-max placement for large-scale timing optimization.	ISPD	2002	DBLP DOI BibTeX RDF
1	Jordi Cortadella	Bi-Decomposition and Tree-Height Reduction for Timing Optimization.	IWLS	2002	DBLP BibTeX RDF