| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ang-Chih Hsieh, TingTing Hwang |
TSV Redundancy: Architecture and Design Issues in 3-D IC.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang-Chih Hsieh, Yi-Ta Wu, Shau-Yin Tseng, TingTing Hwang |
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms. |
ICPP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang |
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang |
A physical-location-aware fault redistribution for maximum IR-drop reduction. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsien-Te Chen, Hong-Long Lin, Zi-Cheng Wang, TingTing Hwang |
A new architecture for power network in 3D IC. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Shih-Liang Chen, TingTing Hwang, Shu-Ming Chang, Wen-Wei Lin |
A Fast Digital Chaotic Generator for Secure Communication. |
I. J. Bifurcation and Chaos |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Wen Hsieh, S.-L. Chen, I-Sheng Lin, TingTing Hwang |
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang |
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Liang Chen, TingTing Hwang, Wen-Wei Lin |
Randomness Enhancement Using Digitalized Modified Logistic Map. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li |
TSV redundancy: Architecture and design issues in 3D IC. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang |
Skew-aware polarity assignment in clock tree. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
peak current, polarity assignment, power/ground noise, Clock skew, clock tree |
| 1 | Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma |
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
low-power design, process variations, leakage current, Body biasing |
| 1 | Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang |
New spare cell design for IR drop minimization in Engineering Change Order. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
spare cell, IR drop, decoupling capacitor, ECO |
| 1 | Wen-Wen Hsieh, TingTing Hwang |
Thermal-aware post compilation for VLIW architectures. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang-Chih Hsieh, TingTing Hwang |
Thermal-aware memory mapping in 3D designs. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang |
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shih-Liang Chen, Shu-Ming Chang, Wen-Wei Lin, TingTing Hwang |
Digital Secure-Communication Using Robust Hyper-Chaotic Systems. |
I. J. Bifurcation and Chaos |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang |
Synthesis of a novel timing-error detection architecture. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
fault tolerance, Logic synthesis |
| 1 | Po-Yuan Chen, Che-Yu Liu, TingTing Hwang |
Transition-aware decoupling-capacitor allocation in power noise reduction. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang |
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
DSTN, low power, MTCMOS, sleep transistor |
| 1 | Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang |
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. |
The Journal of Supercomputing |
2007 |
DBLP DOI BibTeX RDF |
Scheduling, Parallel processing, Power management, Dynamic voltage scaling, Power gating, Security processor |
| 1 | Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang |
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Yu Liu, TingTing Hwang |
Crosstalk-Aware Domino-Logic Synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu |
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang |
Skew aware polarity assignment in clock tree. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
Decomposition of instruction decoders for low-power designs. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
instruction decoder, Low power |
| 1 | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang |
Crosstalk minimization in logic synthesis for PLAs. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
synthesis, Crosstalk, PLA, domino logic |
| 1 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
A power-driven multiplication instruction-set design method for ASIPs. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang |
Instruction buffering for nested loops in low-power design. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang |
Switching-activity driven gate sizing and Vth assignment for low power design. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Yu Liu, TingTing Hwang |
Crosstalk-aware domino logic synthesis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu |
Performance-driven crosstalk elimination at post-compiler level. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang |
A bus architecture for crosstalk elimination in high performance processor design. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
instruction/data bus, architecture, high performance, crosstalk |
| 1 | Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu |
Functionality directed clustering for low power MTCMOS design. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu |
Low-power techniques for network security processors. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
A power-driven multiplication instruction-set design method for ASIPs. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Te Ho, TingTing Hwang |
Low power design using dual threshold voltage. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
Decomposition of Instruction Decoder for Low Power Design. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang |
Crosstalk Minimization in Logic Synthesis for PLA. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi-Wei Hu, TingTing Hwang |
Output-pattern directed decomposition for low power design. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang |
Power-Aware Scheduling for Parallel Security Processors with Analytical Models. |
LCPC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai |
Compiler optimization on VLIW instruction scheduling for low power. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers |
| 1 | MingHung Lee, TingTing Hwang, Shi-Yu Huang |
Decomposition of Extended Finite State Machine for Low Power Design. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu |
Logic transformation for low-power synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
logic transformation, power estimation model, low power, Logic synthesis |
| 1 | Chi Ta Wu, TingTing Hwang |
Instruction buffering for nested loops in low power design. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
Architecture driven circuit partitioning. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | LiYi Lin, Yi-Yu Liu, TingTing Hwang |
A construction of minimal delay Steiner tree using two-pole delay model. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu |
Binary decision diagram with minimum expected path length. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai |
Compiler Optimization on Instruction Scheduling for Low Power. |
ISSS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | How-Rern Lin, TingTing Hwang |
On determining sensitization criterion in an iterative gate sizing process. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang |
A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu |
Logic Transformation for Low Power Synthesis. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, TingTing Hwang |
Layout Driven Selection and Chaining of Partial Scan Flip-Flops. |
J. Electronic Testing |
1998 |
DBLP DOI BibTeX RDF |
design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization |
| 1 | Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang |
A Re-engineering Approach to Low Power FPGA Design Using SPFD. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
Architecture driven circuit partitioning. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang |
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Hua Wang, TingTing Hwang |
Boolean matching for incompletely specified functions. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
Low Power FPGA Design - A Re-engineering Approach. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu |
Low power realization of finite state machines - a decomposition approach. |
ACM Trans. Design Autom. Electr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
decomposition of finite state machines, lower power design, state assignment |
| 1 | Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang |
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Hua Wang, TingTing Hwang, Cheng Chen |
Exploiting communication complexity for Boolean matching. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang |
Layout Driven Selecting and Chaining of Partial Scan. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin |
Combining technology mapping and placement for delay-minimization in FPGA designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Hua Wang, TingTing Hwang |
Boolean Matching for Incompletely Specified Functions. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | How-Rern Lin, TingTing Hwang |
Power recduction by gate sizing with path-oriented slack calculation. |
ASP-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang |
Logic synthesis for field-programmable gate arrays. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin |
Performance-driven interconnection optimization for microarchitecture synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang |
Cell Height Driven Transistor Sizing in a Cell Based Module Design. |
EDAC-ETC-EUROASIC |
1994 |
DBLP BibTeX RDF |
|
| 1 | How-Rern Lin, TingTing Hwang |
Dynamical identification of critical paths for iterative gate sizing. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin |
State Assignment for Power and Area Minimization. |
ICCD |
1994 |
DBLP BibTeX RDF |
|
| 1 | Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin |
Combining technology mapping and placement for delay-optimization in FPGA designs. |
ICCAD |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang |
ELM-A Fast Addition Algorithm Discovered by a Program. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
simple processors tree, addition algorithm, ELM, augend, addend, VLSI CAD tool, CMOS VLSI circuits, computational complexity, digital arithmetic, FACTOR |
| 1 | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin |
Efficiently computing communication complexity for multilevel logic synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin |
Exploiting communication complexity for multilevel logic synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin |
Multi-Level Logic Synthesis Using Communication Complexity. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
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