| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Charles Thangaraj, Robert Pownall, Phil Nikkel, Guangwei Yuan, Kevin L. Lear, Tom Chen |
Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery.  |
IEEE Trans. VLSI Syst.  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Thangaraj, Alkan Cengiz, Tom Chen |
Rapid design space exploration using legacy design data and technology scaling trend. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Zach Cashero, Allen Chen, Ryan Hoppal, Tom Chen |
Fast Evaluation of Analog Circuits Using Linear Programming. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Allen Chen, Ryan Hoppal, Tom Chen |
On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Thangaraj, Tom Chen |
Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
pareto-front, What-if analysis, Power-performance trade-off |
| 1 | Charles Thangaraj, Tom Chen |
Design target exploration for meeting time-to-market using pareto analysis. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniela De Venuto, Tom Chen |
Editorial. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Thangaraj, Tom Chen |
Power andPerformance Analysis for Early Design Space Exploration. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
Power-performance tradeoff, What-if analysis |
| 1 | Jayashree Sridharan, Tom Chen |
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayashree Sridharan, Tom Chen |
Modeling multiple input switching of CMOS gates in DSM technology using HDMR. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniela De Venuto, Tom Chen |
International Symposium on Quality Electronic Design. |
Microelectronics Journal |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Medha Kulkarni, Tom Chen |
A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinil Varghese, Tom Chen, Peter Young |
Stability analysis of active clock deskewing systems using a control theoretic approach. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | John Pratt, Mahir Aydin, Tom Chen |
RC Extraction of Interconnects at Sub-Wavelength Dimensions. |
Artificial Intelligence and Applications |
2005 |
DBLP BibTeX RDF |
|
| 1 | Vinil Varghese, Tom Chen, Peter Michael Young |
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajith Chandy, Tom Chen |
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Amjad Hajjar |
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Geun Rae Cho, Tom Chen |
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerald Esch Jr., Tom Chen |
Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Medha Kulkarni, Tom Chen |
A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerald Esch Jr., Tom Chen |
Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen |
RUBASTEM: A Method for Testing VHDL Behavioral Models. |
HASE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinsang Kim, Tom Chen |
A VLSI architecture for video-object segmentation. |
IEEE Trans. Circuits Syst. Video Techn. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Geun Rae Cho, Tom Chen |
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Amjad Hajjar |
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen |
A Rule-Based Software Testing Method for VHDL Models. |
VLSI-SOC |
2003 |
DBLP BibTeX RDF |
|
| 1 | Geun Rae Cho, Tom Chen |
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson |
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
anti-random testing, code coverage improvement, test data generation |
| 1 | Amjad Hajjar, Tom Chen |
Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
Behavioral Model Verification, VHDL, Stopping Criteria |
| 1 | Geun Rae Cho, Tom Chen |
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic |
| 1 | Amjad Hajjar, Tom Chen |
An Accurate Coverage Forecasting Model for Behavioral Model Verification. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
Behavioral model verification, Statistical stopping rules, VHDL |
| 1 | Geun Rae Cho, Tom Chen |
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. |
IWLS |
2002 |
DBLP BibTeX RDF |
|
| 1 | Geun Rae Cho, Tom Chen |
On The Impact of Technology Scaling On Mixed PTL/Static Circuits. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinsang Kim, Tom Chen |
Multiple feature clustering for image sequence segmentation. |
Pattern Recognition Letters |
2001 |
DBLP BibTeX RDF |
|
| 1 | Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman |
Stopping Criteria Comparison: Towards High Quality Behavioral Verification. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen |
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinsang Kim, Tom Chen |
Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture. |
VIIP |
2001 |
DBLP BibTeX RDF |
|
| 1 | Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman |
High quality behavioral verification using statistical stopping criteria. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
behavioral model verification, statistical stopping rules, VHDL |
| 1 | Tom Chen |
On the impact of on-chip inductance on signal nets under the influence of power grid noise. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu |
Achieving the Quality of Verification for Behavioral Models with Minimum Effort. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
behavioral model verification, Compound Poisson, effort-domain, empirical Bayesian analysis, negative binomial distribution(NBD), Poisson LSD, testing strategy, stopping rule |
| 1 | Jinsang Kim, Tom Chen |
Segmentation of Image Sequences Using SOFM Networks. |
ICPR |
2000 |
DBLP DOI BibTeX RDF |
image sequence segmentation, neural network, motion estimation, MPEG-4, region merging |
| 1 | Jinsang Kim, Tom Chen |
A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
image sequence segmentation, edge fusion, VLSI edge fusion architecture, segmentation, image sequences, image sequences, VLSI architecture, complexity analysis, gray level |
| 1 | Amjad Hajjar, Tom Chen |
VLSI Architecture for Real-Time Edge Linking. |
IEEE Trans. Pattern Anal. Mach. Intell. |
1999 |
DBLP DOI BibTeX RDF |
edge linking, VLSI, real-time image processing |
| 1 | Von-Kyoung Kim, Tom Chen |
On comparing functional fault coverage and defect coverage for memory testing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Glen Sunada, Jain Jin |
COBRA: a 100-MOPS single-chip programmable and expandable FFT. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu |
How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing. (PDF / PS) |
HASE |
1999 |
DBLP DOI BibTeX RDF |
Behavioral Model Testing, Compound Poisson, Effort-Domain, Empirical Bayesian Analysis, Negative Binomial Distribution (NBD), Poisson LSD, Testing Strategy, Stopping Rule |
| 1 | Von-Kyoung Kim, Tom Chen |
Assessing Defect Coverage of Memory Testing Algorithms. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Von-Kyoung Kim, Tom Chen, Mick Tegethoff |
Fault Coverage Estimation for Early Stage of VLSI Design. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar |
Efficient Verification of Behavioral Models Using Sequential Sampling Technique. |
VLSI |
1999 |
DBLP BibTeX RDF |
|
| 1 | Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar |
Fast Antirandom (FAR) Test Generation. (PDF / PS) |
HASE |
1998 |
DBLP DOI BibTeX RDF |
Antirandom test generation, generation efficiency, test coverage |
| 1 | Fahad M. Alzahrani, Tom Chen |
A Real-Time Edge Detector: Algorithm and VLSI Architecture. |
Real-Time Imaging |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Mick Tegethoff, Tom Chen |
Simulation Techniques for the Manufacturing Test of MCMs. |
J. Electronic Testing |
1997 |
DBLP DOI BibTeX RDF |
simulation, test, DFT, yield, DFM, SMT, MCM, board |
| 1 | Von-Kyoung Kim, Tom Chen, Mick Tegethoff |
ASIC Manufacturing Test Cost Prediction at Early Design Stage. |
ITC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Chien-Chih Chen, Tom Chen |
Modified Rate-Distortion Function with Optimal Classification for Wavelet Coding. (PDF / PS) |
ICIP |
1997 |
DBLP DOI BibTeX RDF |
optimal classification, hybrid optimum classification, modified rate-distortion function, wavelet transform based coding, upper band subimage, minimum quantization error, efficient prediction model, asymptotic rate-distortion function, classified VQ, computation load reduction, biorthogonal wavelet filter, wavelet transforms, prediction model, performance comparison, wavelet decomposition, bit allocation, low bit rates |
| 1 | Mick Tegethoff, Tom Chen |
Sensitivity Analysis of Critical Parameters in Board Test. |
IEEE Design & Test of Computers |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Von-Kyoung Kim, Mick Tegethoff, Tom Chen |
ASIC Yield Estimation at Early Design Cycle. |
ITC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Anderson, Anneliese von Mayrhauser, Tom Chen |
Assessing Neural Networks as Guides for Testing Activities. (PDF / PS) |
IEEE METRICS |
1996 |
DBLP DOI BibTeX RDF |
test case effectiveness, test guidance, neural networks |
| 1 | Mick Tegethoff, Tom Chen |
Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. |
ITC |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Mick Tegethoff, Tom Chen |
Defects, Fault Coverage, Yield and Cost in Board Manufacturing. |
ITC |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Glen Sunada, Jain Jin, Matt Berzins, Tom Chen |
COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. |
ICCD |
1994 |
DBLP BibTeX RDF |
|
| 1 | Fahad M. Alzahrani, Tom Chen |
On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. |
ICCD |
1994 |
DBLP BibTeX RDF |
|
| 1 | Tom Chen, Glen Sunada |
Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. |
IEEE Trans. VLSI Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Li Zhu |
An expandable column fft architecture using circuit switching networks. |
VLSI Signal Processing |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Glen Sunada |
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. |
ITC |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Chen, Glen Sunada |
An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. |
ICCD |
1992 |
DBLP BibTeX RDF |
|
| 1 | Tom Chen, Li Zhu |
A Fast 1024-Point FFT Architecture. |
ICPP |
1991 |
DBLP BibTeX RDF |
|
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