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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 24 occurrences of 18 keywords
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Results
Found 37 publication records. Showing 37 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee |
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.  |
Integration  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee |
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee |
The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B. |
Journal of Circuits, Systems, and Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee |
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai |
Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. |
J. Inf. Sci. Eng. |
2010 |
DBLP BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee |
Antenna Violation Avoidance/Fixing for X-clock routing. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee |
Double-via insertion enhanced X-architecture clock routing for reliability. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee |
The Design of a Li-ion Battery Charger Based on Multimode LDO Technology. |
Journal of Circuits, Systems, and Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee |
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. |
Journal of Circuits, Systems, and Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee |
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee |
Layer assignment considering manufacturability in X-architecture clock tree. |
CIT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao |
X-clock routing based on pattern matching. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee |
Zero-Skew Driven Buffered RLC Clock Tree Construction. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao |
Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems. |
IIH-MSP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao |
An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. |
IMECS |
2007 |
DBLP BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu |
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. |
J. Inf. Sci. Eng. |
2006 |
DBLP BibTeX RDF |
|
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai |
Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. |
ICICIC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee |
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao |
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao |
A single chip image sensor embedded smooth spatial filter with A/D conversion. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao |
Coupling aware RLC-based clock routings for crosstalk minimization. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Pao-Ann Hsiung, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See |
SESAG: an object-oriented application framework for real-time systems. |
Softw., Pract. Exper. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang |
A new low-power turbo decoder using HDA-DHDD stopping iteration. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen |
A new CCII-based pipelined analog to digital converter. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee |
Zero-Skew Driven for RLC Clock Tree Construction in SoC. |
ICITA |
2005 |
DBLP DOI BibTeX RDF |
RLC delay model, Upward propagation, SoC, Clock tree, Zero skew |
| 1 | Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See |
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software. |
IEEE Trans. Software Eng. |
2004 |
DBLP DOI BibTeX RDF |
embedded real-time software, scheduling, formal verification, code generation, software components, Application framework, UML modeling, formal synthesis |
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang |
RCGES: Retargetable Code Generation for Embedded Systems. |
ATVA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Win-Bin See, Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen |
Software Platform for Embedded Software Development. |
RTCSA |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Pao-Ann Hsiung, I-Mu Wu, Feng-Shi Su |
RESS: Real-Time Embedded Software Synthesis and Prototyping Methodology. |
RTCSA |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Pao-Ann Hsiung, Cheng-Yi Lin, Trong-Yen Lee |
Quasi-Dynamic Scheduling for the Synthesis of Real-Time Embedded Software with Local and Global Deadlines. |
RTCSA |
2003 |
DBLP DOI BibTeX RDF |
Periodic Time Petri Nets, quasi-dynamic scheduling, local and global deadlines, software synthesis, Real-time embedded software |
| 1 | Pao-Ann Hsiung, Trong-Yen Lee, Feng-Shi Su |
Formal Synthesis and Code Generation of Real-Time Embedded Software using Time-Extended Quasi-Static Scheduling. |
APSEC |
2002 |
DBLP DOI BibTeX RDF |
Time Complex-Choice Petri Nets, time-extended quasi-static scheduling, code generation, real-time embedded software |
| 1 | Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen |
TCN: Scalable Hierarchical Hypercubes. |
ICPADS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Pao-Ann Hsiung, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, Sao-Jie Chen |
VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems. (PDF / PS) |
Symposium on Object-Oriented Real-Time Distributed Computing |
2002 |
DBLP DOI BibTeX RDF |
object-oriented, formal verification, code generation, software component, embedded real-time systems |
| 1 | Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen |
Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks. |
APSEC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen |
A Case Study in Hardware-Software Codesign of Distributed Systems - Vehicle Parking Management System. |
PDPTA |
1999 |
DBLP BibTeX RDF |
|
| 1 | Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen |
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
concurrent object-oriented system-level synthesis, fuzzy design-space exploration, learning |
| 1 | Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen |
Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis. |
TOOLS |
1997 |
DBLP DOI BibTeX RDF |
Learning, Synthesis, Object-Oriented Modeling, Design Management |
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