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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 28 publication records. Showing 28 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To |
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Yuan-Ho Chen, Tsin-Yuan Chang |
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Yuan-Ho Chen, Tsin-Yuan Chang |
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers. |
IEEE Trans. on Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li |
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen |
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang |
Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang |
A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Po-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang |
IEEE Standard 1500 Compatible Delay Test Framework. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Hung-Chih Lin, Hsiang-Han Wu, Tsin-Yuan Chang |
An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang |
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Hung-Chih Lin, Bou-Ching Fung, Tsin-Yuan Chang |
A current mode adaptive on-time control scheme for fast transient DC-DC converters. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Chung-Yi Li, Jiung-Sheng Chen, Tsin-Yuan Chang |
A chaos-based pseudo random number generator using timing-based reseeding method. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang |
On-chip accumulated jitter measurement for phase-locked loops. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang |
A Built-In Parametric Timing Measurement Unit. |
IEEE Design & Test of Computers |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang |
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang |
Timing measurement unit with multi-stage TVC for embedded memories. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong |
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang |
An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang |
An Access Timing Measurement Unit of Embedded Memory. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang |
A built-in timing parametric measurement unit. |
ITC |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang |
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang |
A low-cost CMOS time interval measurement core. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Tsin-Yuan Chang, Yervant Zorian |
SoC Testing and P1500 Standard. (PDF / PS) |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang |
A realistic fault model for flash memories. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
NAND circuits, faulty behavior classification, NAND-type flash memory, SPICE models, flash cell models, circuit-level faulty behavior simulation, testing, fault model, fault modeling, fault simulation, flash memories, flash memories, circuit analysis computing, SPICE, integrated memory circuits |
| 1 | Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang |
A Programmable BIST Core for Embedded DRAM. |
IEEE Design & Test of Computers |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Chin-Long Wey, Tsin-Yuan Chang |
An efficient output phase assignment for PLA minimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1990 |
DBLP DOI BibTeX RDF |
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| 1 | Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang |
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
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| 1 | Chin-Long Wey, Tsin-Yuan Chang |
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. |
DAC |
1988 |
DBLP BibTeX RDF |
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