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Publications of "Tsuneo Nakata" ( http://dblp.L3S.de/Authors/Tsuneo_Nakata )

  Author page on DBLP  Author page in RDF  Community of Tsuneo Nakata in ASPL-2

Publication years (Num. hits)
1994-2005 (12)
Publication types (Num. hits)
article(1) inproceedings(11)
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The graphs summarize 15 occurrences of 12 keywords

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Found 12 publication records. Showing 12 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata Integrating UML into SoC Design Process. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro Kuroki, Yoichi Endo, Takashi Hasegawa System-on-Chip Verification Process Using UML. Search on Bibsonomy UML Satellite Activities The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata System-on-chip validation using UML and CWL. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF specification modeling, UML, validation and verification, verification process
1Tsuneo Nakata Multi-event algorithms and protocols for fast and robust distributed mesh provisioning and restoration. Search on Bibsonomy Bell Labs Technical Journal The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu An Object-Oriented Design Process for System-on-Chip Using UML. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF system level performance evaluation, UML, design process, system level design, object-oriented analysis and design
1Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Kwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata A Method of Static Compaction of Test Stimuli. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata Formal verification based on assume and guarantee approach - a case study (short paper). Search on Bibsonomy ASP-DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata Dataflow Analysis for Resource Contention and Register Leakage Properties. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Register Leakage, Simulation, Formal Verification, Resource Contention
1Hiroaki Iwashita, Tsuneo Nakata Forward model checking techniques oriented to buggy designs. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF symbolic state traversal, forward model checking, formal verification, symbolic model checking
1Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose CTL model checking based on forward state traversal. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF state traversal, partitioned transition relation, model checking, formal verification, CTL
1Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose Automatic test program generation for pipelined processors. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
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