|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 15 occurrences of 12 keywords
|
|
|
|
|
Results
Found 12 publication records. Showing 12 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata |
Integrating UML into SoC Design Process.  |
DATE  |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro Kuroki, Yoichi Endo, Takashi Hasegawa |
System-on-Chip Verification Process Using UML.  |
UML Satellite Activities  |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata |
System-on-chip validation using UML and CWL.  |
CODES+ISSS  |
2004 |
DBLP DOI BibTeX RDF |
specification modeling, UML, validation and verification, verification process |
| 1 | Tsuneo Nakata |
Multi-event algorithms and protocols for fast and robust distributed mesh provisioning and restoration.  |
Bell Labs Technical Journal  |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu |
An Object-Oriented Design Process for System-on-Chip Using UML.  |
ISSS  |
2002 |
DBLP DOI BibTeX RDF |
system level performance evaluation, UML, design process, system level design, object-oriented analysis and design |
| 1 | Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan |
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).  |
VLSI Design  |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata |
A Method of Static Compaction of Test Stimuli.  |
Asian Test Symposium  |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata |
Formal verification based on assume and guarantee approach - a case study (short paper).  |
ASP-DAC  |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata |
Dataflow Analysis for Resource Contention and Register Leakage Properties.  |
VLSI Design  |
2000 |
DBLP DOI BibTeX RDF |
Register Leakage, Simulation, Formal Verification, Resource Contention |
| 1 | Hiroaki Iwashita, Tsuneo Nakata |
Forward model checking techniques oriented to buggy designs.  |
ICCAD  |
1997 |
DBLP DOI BibTeX RDF |
symbolic state traversal, forward model checking, formal verification, symbolic model checking |
| 1 | Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose |
CTL model checking based on forward state traversal.  |
ICCAD  |
1996 |
DBLP DOI BibTeX RDF |
state traversal, partitioned transition relation, model checking, formal verification, CTL |
| 1 | Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose |
Automatic test program generation for pipelined processors.  |
ICCAD  |
1994 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #12 of 12 (100 per page; Change: )
|
|