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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 12 occurrences of 8 keywords
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Results
Found 36 publication records. Showing 36 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jing-Wei Lin, Tsung-Yi Ho, Iris Hui-Ru Jiang |
Reliability-Driven Power/Ground Routing for Analog ICs.  |
ACM Trans. Design Autom. Electr. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Jia-Wen Chang, Tsung-Yi Ho |
Integrated fluidic-chip co-design methodology for digital microfluidic biochips. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho |
An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chips. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho |
A cyberphysical synthesis approach for error recovery in digital microfluidic biochips. |
DATE |
2012 |
DBLP BibTeX RDF |
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| 1 | Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho |
An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho |
A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Tsung-Yi Ho |
A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho |
Pulsed-latch-based clock tree migration for dynamic power reduction. |
ISLPED |
2011 |
DBLP BibTeX RDF |
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| 1 | Po-Hsun Wu, Tsung-Yi Ho |
Thermal-aware bus-driven floorplanning. |
ISLPED |
2011 |
DBLP BibTeX RDF |
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| 1 | Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang |
A SAT-based routing algorithm for cross-referencing biochips. |
SLIP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Charles Chiang, Tsung-Yi Ho |
A distributed algorithm for layout geometry operations. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Tsung-Wei Huang, Hong-Yan Su, Tsung-Yi Ho |
Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho |
An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Ling Hsieh, Tsung-Yi Ho |
Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Yan-You Lin, Jia-Wen Chang, Tsung-Yi Ho |
Recent research and emerging challenges in design and optimization for digital microfluidic biochips. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu |
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Tsung-Wei Huang, Tsung-Yi Ho, Krishnendu Chakrabarty |
Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Krishnendu Chakrabarty, Paul Pop, Tsung-Yi Ho |
Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Tsung-Yi Ho, Krishnendu Chakrabarty, Paul Pop |
Digital microfluidic biochips: recent research and emerging challenges. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho |
A Contamination Aware Droplet Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho, Sheng-Hung Liu |
Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho, Sheng-Hung Liu |
Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization. |
VLSI-SoC (Selected Papers) |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo-Shiun Wu, Tsung-Yi Ho |
Bus-pin-aware bus-driven floorplanning. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
bus planning, floorplanning |
| 1 | Tsung-Wei Huang, Tsung-Yi Ho |
A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
routing, ilp, microfluidic, biochip |
| 1 | Tsung-Yi Ho, Jun Zeng, Krishnendu Chakrabarty |
Digital microfluidic biochips: A vision for functional diversity and more than moore. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho |
A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chips. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho |
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheng Chou, Tsung-Yi Ho |
OAL: An obstacle-aware legalization in standard cell placement with displacement minimization. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho |
A contamination aware droplet routing algorithm for digital microfluidic biochips. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Tsung-Yi Ho |
A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho |
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen |
Multilevel routing with jumper insertion for antenna avoidance. |
Integration |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee |
Crosstalk- and performance-driven multilevel full-chip routing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen |
Multilevel full-chip routing for the X-based architecture. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
Xarchitecture, routing, physical design, multilevel optimization |
| 1 | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen |
Multilevel routing with antenna avoidance. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
nanometer, process antenna effect, routing, physical design, design for manufacturability (DFM), multilevel optimization |
| 1 | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee |
A Fast Crosstalk- and Performance-Driven Multilevel Routing System. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
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