Search results for "Two-pattern testing"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Ilia Polian, Bernd Becker	Multiple Scan Chain Design for Two-Pattern Testing.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	scan chain insertion, delay testing, design for test, core-based test
2	Ilia Polian, Bernd Becker	Multiple Scan Chain Design for Two-Pattern Testing.	VTS	2001	DBLP DOI BibTeX RDF	Scan chain insertion, Delay testing, Design for test, Core-based test
2	Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara	LFSR-Based Deterministic TPG for Two-Pattern Testing.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	configurable LFSR, built-in self-test, path delay faults, two-pattern test
2	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An Accumulator-Based BIST Approach for Two-Pattern Testing.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	stuck-open fault testing, built-in self test, delay fault testing, two-pattern testing
2	Xiaowei Li, Paul Y. S. Cheung	Exploiting BIST Approach for Two-Pattern Testing.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
2	Chih-Ang Chen, Sandeep K. Gupta	BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Built-in self-test, cellular automata, linear feedback shift register, test pattern generator, two-pattern testing, pseudo-exhaustive testing
1	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
1	Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi	Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.	DFT	2007	DBLP DOI BibTeX RDF
1	Qiang Xu, Nicola Nicolici	DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	embedded core delay test, System-on-a-chip
1	Ilia Polian, Bernd Becker	Stop & Go BIST.	IOLTW	2002	DBLP DOI BibTeX RDF	Thermal constraints, BIST, Delay testing, IP cores
1	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
1	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Robust Sequential Fault Testing of Iterative Logic Arrays.	VTS	1997	DBLP DOI BibTeX RDF	Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
1	Kiyoshi Furuya, Susumu Yamazaki, Masayuki Sato	Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Kiyoshi Furuya, Seiji Seki, Edward J. McCluskey	Design of Autonomous TPG Circuits for Use in Two-Pattern Testing.	IEICE Transactions	1995	DBLP BibTeX RDF