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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9 occurrences of 6 keywords
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Results
Found 19 publication records. Showing 19 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
Simulation-based equivalence checking between SystemC models at different levels of abstraction.  |
ACM Great Lakes Symposium on VLSI  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Laurent Fribourg, Ulrich Kühne |
Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method. |
RP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
Automatic property generation for the formal verification of bus bridges. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Towards Fully Automatic Synthesis of Embedded Software. |
Embedded Systems Letters |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow |
Automated formal verification of processors based on architectural models. |
FMCAD |
2010 |
DBLP BibTeX RDF |
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| 1 | Ulrich Kühne |
Advanced automation in formal verification of processors. |
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2009 |
RDF |
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| 1 | André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
WoLFram- A Word Level Framework for Formal Verification. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ulrich Kühne, Sven Beyer, Christian Pichler |
Generating an Efficient Instruction Set Simulator from a Complete Property Suite. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
Contradictory antecedent debugging in bounded model checking. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
formal verification, debugging, bounded model checking, psl |
| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Property analysis and design understanding. |
DATE |
2009 |
DBLP BibTeX RDF |
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| 1 | André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
Increasing the accuracy of SAT-based debugging. |
DATE |
2009 |
DBLP BibTeX RDF |
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| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Analyzing Functional Coverage in Bounded Model Checking. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. |
MTV |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Estimating functional coverage in bounded model checking. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Ulrich Kühne, Nicole Drechsler |
Finding Compact BDDs Using Genetic Programming. |
EvoWorkshops |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
HW/SW co-verification of embedded systems using bounded model checking. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
hardware/software co-verification, embedded systems, formal verification, SystemC, bounded model checking, PSL |
| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. |
GI Jahrestagung |
2005 |
DBLP BibTeX RDF |
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| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. |
MTV |
2005 |
DBLP DOI BibTeX RDF |
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