Search results for "Uri C. Weiser"

Found 15 publication records. Showing 15 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser	Task Scheduling Based On Thread Essence and Resource Limitations.	JCP	2012	DBLP DOI BibTeX RDF
1	Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser	Multi-Amdahl: Optimal Resource Sharing with Multiple Program Execution Segments	CoRR	2011	DBLP BibTeX RDF
1	Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman	Memristor-based IMPLY logic design procedure.	ICCD	2011	DBLP DOI BibTeX RDF
1	André Seznec, Uri C. Weiser, Ronny Ronen (eds.)	37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France	ISCA	2010	DBLP BibTeX RDF
1	Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser	Threads vs. caches: Modeling the behavior of parallel workloads.	ICCD	2010	DBLP DOI BibTeX RDF
1	Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser	Many-Core vs. Many-Thread Machines: Stay Away From the Valley.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
1	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
1	A. Elyada, Ran Ginosar, Uri C. Weiser	Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
1	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Nahalal: Cache Organization for Chip Multiprocessors.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé	Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors.	Computer Architecture Letters	2006	DBLP DOI BibTeX RDF
1	Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir	Interconnect-power dissipation in a microprocessor.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect power, wire spacing, routing, low-power design
1	Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser	Correlated Load-Address Predictors.	ISCA	1999	DBLP DOI BibTeX RDF	context-based predictor, global correlation, load-address prediction, predictor implementation, recursive data structures
1	Alex Peleg, Sam Wilkie, Uri C. Weiser	Intel MMX for Multimedia PCs.	Commun. ACM	1997	DBLP DOI BibTeX RDF
1	Fabian Klass, Uri C. Weiser	Efficient Systolic Array for Matrix Multiplication.	ICPP	1991	DBLP BibTeX RDF

Publications of "Uri C. Weiser" ( http://dblp.L3S.de/Authors/Uri_C._Weiser )