| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli |
A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands.  |
J. Electrical and Computer Engineering  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shoaib Mohammed, S. K. Noor Mahammad, V. Kamakoti |
Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. |
Appl. Soft Comput. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthik Raghavan, V. Kamakoti |
ROSY: recovering processor and memory systems from hard errors. |
Operating Systems Review |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti |
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli |
A Simulation Based Buffer Sizing Algorithm for Network on Chips. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti |
Impact of Temperature on Test Quality. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Shyamala, J. Vimalkumar, V. Kamakoti |
Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi |
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Kunal, K. George, M. Gautam, V. Kamakoti |
HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions. |
Operating Systems Review |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi |
Efficient Grouping of Fail Chips for Volume Yield Diagnostics. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti |
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil |
Automatic Constraint Based Test Generation for Behavioral HDL Models. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula |
Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. |
J. Low Power Electronics |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti |
A novel approach to the placement and routing problems for field programmable gate arrays. |
Appl. Soft Comput. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti |
FPGA based Agile Algorithm-On-Demand Co-Processor |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | A. Pavan Kumar, V. Kamakoti, Sukhendu Das |
System-on-programmable-chip implementation for on-line face recognition. |
Pattern Recognition Letters |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Variation-Tolerant, Power-Safe Pattern Generation. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
low-power ATPG, process variation, IR drop, peak power, power profiling |
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti |
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling |
| 1 | K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula |
Power Virus Generation Using Behavioral Models of Circuits. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models |
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula |
Controllability-driven Power Virus Generation for Digital Circuits. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam |
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam |
Delay and peak power minimization for on-chip buses using temporal redundancy. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
low-power, coding, crosstalk |
| 1 | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti |
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti |
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti |
Pseudo-online testing methodologies for various components of field programmable gate arrays. |
Microprocessors and Microsystems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil |
A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan |
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan |
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti |
A function generator-based reconfigurable system. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti |
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan |
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan |
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
Complex Logic Blocks, Routing Errors, Vertex Coloring problem, Fault Tolerance, Field Programmable Gate Arrays, Graph Theory, Single Event Upset |
| 1 | R. Manimegalai, E. Siva Soumya, V. Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia |
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
Three-Dimensional FPGA, Reinforcement Learning (RL), Two-opt algorithm, Support Vector Machines (SVMs), Placement and Routing |
| 1 | Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti |
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti |
A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti |
FPGA based Agile Algorithm-On-Demand Co-Processor. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti |
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti |
An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. |
MICAI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Manoj Kumar, B. Jayaram, R. Manimegalai, V. Kamakoti |
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti |
A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. |
ICONIP |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Pavan Kumar, Sukhendu Das, V. Kamakoti |
Face Recognition Using Weighted Modular Principle Component Analysis. |
ICONIP |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Manoj Kumar, B. Jayaram, V. Kamakoti |
SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar |
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam |
A Bus Encoding Technique for Power and Cross-talk Minimization. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
Cross-talk, Limited Weight Codes, Transition Signalling, Encoding techniques, memoryless bus encoding, pipelining, Low Power Design |
| 1 | A. Manoj Kumar, Jayaram Bobba, V. Kamakoti |
MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Pavan Kumar, V. Kamakoti, Sukhendu Das |
An Architecture for Real Time Face Recognition Using WMPCA. |
ICVGIP |
2004 |
DBLP BibTeX RDF |
|
| 1 | B. Jayaram, A. Manoj Kumar, V. Kamakoti |
Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. |
HiPC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti |
Testable Clock Routing Architecture for Field Programmable Gate Arrays. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Madhu, V. Srinivasa Murty, V. Kamakoti |
Dynamic Coding Technique For Low-Power Data Bus. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti |
A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh |
On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. |
VLSI |
2003 |
DBLP BibTeX RDF |
|
| 1 | Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Ganesh, V. Kamakoti |
A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. |
IICAI |
2003 |
DBLP BibTeX RDF |
|
| 1 | Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti |
A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Srinathan, C. Pandu Rangan, V. Kamakoti |
Toward Optimal Player Weights in Secure Distributed Protocols. |
INDOCRYPT |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | V. Annamalai, C. S. Krishnamoorthy, V. Kamakoti |
Adaptive finite element analysis on a parallel and distributed environment. |
Parallel Computing |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan |
The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries. |
COCOON |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Graf, V. Kamakoti |
Sparse Dominance Queries for Many Points in Optimal Time and Space. |
Inf. Process. Lett. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | V. Kamakoti, N. Balakrishnan |
Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications. (PDF / PS) |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Arvind, V. Kamakoti, C. Pandu Rangan |
Efficient Parallel Algorithms for Permutation Graphs. |
J. Parallel Distrib. Comput. |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan |
An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets. |
Nord. J. Comput. |
1995 |
DBLP BibTeX RDF |
|
| 1 | V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan |
Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees. |
COCOON |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | P. Jagan Mohan, V. Kamakoti, C. Pandu Rangan |
Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension. |
IFIP Congress |
1994 |
DBLP BibTeX RDF |
|
| 1 | V. Kamakoti, C. Pandu Rangan |
An Optimal Algorithm for Reconstructing a Binary Tree. |
Inf. Process. Lett. |
1992 |
DBLP DOI BibTeX RDF |
|
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