Search results for "V. R. Devanathan"

Found 17 publication records. Showing 17 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	V. R. Devanathan, Srinivas Kumar Vooka	Techniques to improve memory interface test quality for complex SoCs.	ITC	2011	DBLP DOI BibTeX RDF
1	V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra	Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	V. R. Devanathan, Ishaan Santhosh Shah	Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	M. A. Maluk Mohamed, V. R. Devanathan, D. Janakiram	EOMP: an exactly once multicast protocol for distributed mobile systems.	IJPEDS	2010	DBLP DOI BibTeX RDF
1	V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar	Towards effective and compression-friendly test of memory interface logic.	ITC	2010	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti	A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	Variation-Tolerant, Power-Safe Pattern Generation.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	low-power ATPG, process variation, IR drop, peak power, power profiling
1	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test.	ITC	2007	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti	PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.	ITC	2007	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
1	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.	DATE	2007	DBLP DOI BibTeX RDF
1	Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji	Methodology for low power test pattern generation using activity threshold control logic.	ICCAD	2007	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	V. R. Devanathan	Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar	A Framework for Distributed and Hierarchical Design-for-Test.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	D. Janaki Ram, M. A. Maluk Mohamed, V. R. Devanathan	A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems.	ICDCS Workshops	2003	DBLP DOI BibTeX RDF	Real-time distributed collaboration, data-centric concurrency control, EOMP, optimistic concurrency control

Publications of "V. R. Devanathan" ( http://dblp.L3S.de/Authors/V._R._Devanathan )