Search results for "VHDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Wilco Van Hoogstraeten, Henk Corporaal	ADVISE: Performance Evaluation of Parallel VHDL Simulation.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	VHDL compilation, VHDL simulation, partitioning, distributed simulation, Optimistic simulation, multiprocessor simulation
4	Peter F. A. Middelhoek, Sreeranga P. Rajan	From VHDL to efficient and first-time-right designs: a formal approach.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	CDFG, SFG, rapid system prototyping, VHDL, VHDL, design methodology, correctness by construction, transformational design
4	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
3	Abdulhadi Shoufan, Zheng Lu, Guido Rößling	A platform for visualizing digital circuit synthesis with VHDL.	ITiCSE	2010	DBLP DOI BibTeX RDF	digital circuit synthesis, visualization, animation, VHDL
3	Mariagrazia Graziano, Massimo Ruo Roch	An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Automotive electro-mechanical test, Fault simulation, VHDL-AMS
3	Fabian Diet, Erik H. D'Hollander, Kristof Beyls, Harald Devos	Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler.	DELTA	2008	DBLP DOI BibTeX RDF	C-to-VHDL compiling, Impulse-C, Smart buffer, FPGA, High-performance computing
3	Sang-Gu Lee, Michio Miyazaki, Jin-Il Kim	Design of Very High-Speed Integer Fuzzy Controller Without Multiplications by Using VHDL.	KES	2007	DBLP DOI BibTeX RDF	Integer operation, VHDL, Fuzzy control, Defuzzification, COG
3	Paul Salama, Maher E. Rizkalla, Michael Eckbauer	VHDL Implementation of the Fast Wavelet Transform.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	Mallat's fast Wavelet Transform, VHDL implementation, VLSI, finite state machine, discrete wavelet transform
3	C. T. Carr, T. Martin McGinnity, L. J. McDaid	Integration of UML and VHDL-AMS for analogue system modelling.	Formal Asp. Comput.	2004	DBLP DOI BibTeX RDF	Analogue, Automated mapping, UML, Circuits, VHDL-AMS
3	Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri	A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis
3	Donald B. Shaw, Dhamin Al-Khalili, Come Rozon	IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	neural networks, VHDL, fault models, fault simulation, CMOS ICs, Bridge defects, IP blocks
3	Régis Leveugle, K. Hadjiat	Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	VHDL, fault injection, VLSI design, dependability analysis, digital circuits
3	Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara	From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.	SBCCI	2003	DBLP DOI BibTeX RDF	transaction level, VHDL, SystemC, System modeling, register transfer level
3	William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza	Early estimation of the size of VHDL projects.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	VHDL analysis, embedded systems, cost estimation, system-level design, design metrics
3	Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee	Automatic Parallelization of Compiled Event Driven VHDL Simulation.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	scheduling, partitioning, VHDL, multithreading, automatic parallelization, event driven simulation, compiled simulation
3	Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum	Program slicing for VHDL.	STTT	2002	DBLP DOI BibTeX RDF	Model checking, Formal verification, VHDL, Program slicing, Hardware description languages
3	S. M. Aziz, C. N. Basheer, Joarder Kamruzzaman	A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier.	DELTA	2002	DBLP DOI BibTeX RDF	Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable
3	Haifeng Zhou, Zhenghui Lin, Wei Cao	Research on VHDL RTL Synthesis System.	DELTA	2002	DBLP DOI BibTeX RDF	VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser
3	Régis Leveugle, K. Hadjiat	Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study.	IOLTW	2002	DBLP DOI BibTeX RDF	VHDL, fault injection, VLSI design, dependability analysis
3	Sumit Ghosh	P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
3	Régis Leveugle, R. Cercueil	High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	circuit architectures, fault tolerance, VHDL, on-line testing
3	Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil	Comparison and Application of Different VHDL-Based Fault Injection Techniques. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	VHDL-Based Fault Injection, Fault Tolerant Validation
3	B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	New Techniques for Accelerating Fault Injection in VHDL Descriptions.	IOLTW	2000	DBLP DOI BibTeX RDF	VHDL, Fault Injection
3	Frédéric Mallet, Daniel Gaffé, Fernand Boéri	Concurrent Control Systems: From Grafcet to VHDL.	EUROMICRO	2000	DBLP DOI BibTeX RDF	GRAFCET, programmable components, Modelling, FPGA, Specification, VHDL
3	Stanislaw Deniziak, Krzysztof Sapiecha	High Level Testbench Generation for VHDL Models.	ECBS	1999	DBLP DOI BibTeX RDF	simulation, VHDL, testbench
3	William E. McUmber, Betty H. C. Cheng	UML-Based Analysis of Embedded Systems Using a Mapping to VHDL. (PDF / PS)	HASE	1999	DBLP DOI BibTeX RDF	formal specifications, mappings, VHDL, Object-oriented modeling
3	Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong	FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking.	ASP-DAC	1999	DBLP DOI BibTeX RDF	Finite State Machine, VHDL, Symbolic Model Checking
3	Nouma Izeboudjen, Ahcene Farah, S. Titri, H. Boumeridja	Digital Implementation of Artificial Neural Networks: From VHDL Description to EPGA Implementation.	IWANN	1999	DBLP DOI BibTeX RDF	parametric description, ANN, VHDL, FPGA implementation, top down design
3	Oliver Bringmann, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann	Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL
3	Michael V. Goncharov, Alexander B. Smirnov, Nikolai Starodoubtsev, Ilya V. Klotchkov	Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment.	ACSD	1998	DBLP DOI BibTeX RDF	asynchronous circuits' design, simulation, VHDL, Signal Transition Graph (STG)
3	Eduard Moser, Norbert Mittwollen	VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive Engineering.	DATE	1998	DBLP DOI BibTeX RDF	Mixed-Domain Modelling, Mixed-Domain Simulation, Automotive Engineering, VHDL-AMS
3	Michael Mrva	Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL.	DATE	1998	DBLP DOI BibTeX RDF	object-oriented, VHDL, hardware description language
3	Matthias Mutz	Register Transfer Level VHDL Models without Clocks.	DATE	1998	DBLP DOI BibTeX RDF	VHDL RT subset, register transfer level models
3	Edwin Naroska	Parallel VHDL Simulation.	DATE	1998	DBLP DOI BibTeX RDF	Conservative Parallel VHDL simulation, parallel discrete event simulation, PDES
3	Serafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba	VHDL Teamwork, Organization Units and Workspace Management.	DATE	1998	DBLP DOI BibTeX RDF	VHDL analysis, simulation, management, Teamwork, cooperative work, workspace, elaboration
3	Jason Coppens, Dhamin Al-Khalili, Come Rozon	VHDL Modelling and Analysis of Fault Secure Systems.	DATE	1998	DBLP DOI BibTeX RDF	Verification, VHDL, Defect Modelling, Fault Security
3	Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen	The Design of an Asynchronous VHDL Synthesizer.	DATE	1998	DBLP DOI BibTeX RDF	Synthesis, VHDL, Asynchronous
3	Daniel Gil, Juan Carlos Baraza, J. V. Busquets, Pedro J. Gil	Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System.	EUROMICRO	1998	DBLP DOI BibTeX RDF	VHDL simulation, Error syndrome, Propagation latency, Fault injection, Transient faults, Experimental validation
3	Peter T. Breuer, Carlos Delgado Kloos, Andrés Marín López, Natividad Martínez Madrid, Luis Sánchez Fernández	A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	timed logic, formal verification, refinement, VHDL, denotational semantics, digital circuits, program logic
3	Matthias Bauer, Wolfgang Ecker	Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach.	DAC	1997	DBLP DOI BibTeX RDF	VHDL
3	Sien-An Ong, Kari Tiensyrjä, Lech Józwiak	Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models.	EUROMICRO	1997	DBLP DOI BibTeX RDF	interactive codesign, real-time embedded control systems, task graph generation, InCo, textual functional specification method, linear control structures, static behavioral analysis, graphical functional specification method, high level synthesis, finite-state machines, VHDL, modular design, hierarchical decomposition, hardware software partitioning, cost-efficient
3	Come Rozon	On the Use of VHDL as a Multi-Valued Logic Simulator. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications
3	Venkatram Krishnaswamy, Prithviraj Banerjee	Actor Based Parallel VHDL Simulation Using Time Warp.	Workshop on Parallel and Distributed Simulation	1996	DBLP DOI BibTeX RDF	VHDL, Time Warp, Parallel Discrete Event Simulation
3	Michael Münch, Manfred Glesner, Norbert Wehn	An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	control-flow dominated VHDL, time-constrainted scheduling, scheduling, ILP, code transformation, resource-constrained scheduling
3	Sheetanshu L. Pandey, Kothanda R. Subramanian, Philip A. Wilsey	A Semantic Model of VHDL for Validating Rewriting Algebras.	EUROMICRO	1996	DBLP DOI BibTeX RDF	rewriting algebras validation, declarative style, process-folding, CAD tool optimization, VHDL, formal model, semantic model, hardware description languages, interval temporal logic, dynamic semantics
3	Peter Walker, Sumit Ghosh	On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	timing constructs, simulation of hardware descriptions, discrete event simulation, VHDL, Digital simulation, logic Simulation, Timing semantics
3	Nelson L. Passos, Edwin Hsing-Mean Sha	Synthesis of Multi-Dimensional Applications in VHDL. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	Multidimensional Loops, Scheduling, VHDL, Circuit Optimization, Address generation
3	Gunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser	Basic concepts for an HDL reverse engineering tool-set.	ICCAD	1996	DBLP DOI BibTeX RDF	VHDL Verilog Hardware Description Reuse Reverse Engineering Hypertext CASE Visualization Productivity Design Process Analysis Control Flow ADA Graphical Symbol, VHDL
3	Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell	Automated verification of temporal properties specified as state machines in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automated verification methodology, correctness specifications, Viper microprocessor, Mealy FSM, compatible states, formal specification, formal verification, high level synthesis, finite state machines, VHDL, sequential circuits, state machines, hardware description languages, microprocessor chips, synchronous sequential circuit, temporal properties, liveness properties
3	Ali Assi, Bozena Kaminska	Modeling of communication protocols in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	ISO/CCITT class O, VLSI, VLSI, high level synthesis, VHDL, transport protocols, transport protocol, communication protocols, hardware description languages, hardware implementations, high level design, ISO standards
3	Preeti Ranjan Panda, Nikil D. Dutt	1995 high level synthesis design repository.	ISSS	1995	DBLP DOI BibTeX RDF	1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
3	Frank Vahid	Procedure exlining: a transformation for improved system and behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	VHDL transformation tool, distinct computation, procedure exlining, procedure inlining, redundant sequences, statements, formal specification, distributed processing, VHDL, hardware description languages, remote procedure calls, behavioral synthesis, behavioral specification, system synthesis, procedure calls, synthesis tools
2	Md. Rezwanul Ahsan, Muhammad Ibn Ibrahimy, Othman Omran Khalifa	VHDL Modelling of Fixed-point DWT for the Purpose of EMG Signal Denoising.	CICSyN	2011	DBLP DOI BibTeX RDF	Daubechies, VHDL, DWT, Fixed-point, Electromyography
2	Hassan Bajwa, Isaac Macwan, Vignesh Veerapandian, Xinghao Chen	VHDL Implementation of High-Performance and Dynamically Configures Multi-port Cache Memory.	ITNG	2010	DBLP DOI BibTeX RDF	Dynamically configured memory, Multi-port Cache Architecture, VHDL, SRAM
2	Marc Schlickling, Markus Pister	Semi-automatic derivation of timing models for WCET analysis.	LCTES	2010	DBLP DOI BibTeX RDF	vhdl, worst-case execution time, hard real-time
2	Robert Meagher, Modukuri Sushmitha, Maher E. Rizkalla, Paul Salama, Mohamed El-Sharkawy	VHDL Design for Real Time Motion Estimation Video Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	simulation, Real time, Motion estimation, Hardware, Video compression
2	Hongli Tian, Shuo Shi, Jun Zhang, Hongdong Zhao	Controllable Arbitrary Integer Frequency Divider Based on VHDL.	JCAI	2009	DBLP DOI BibTeX RDF	50% duty cycle, frequency divider, FPGA, VHDL, CPLD
2	Barry Schulz, Chirag Parikh, Christian Trefftz	Opportunities for parallelism when implementing algorithms in VHDL - a case study - Shift-Or.	EIT	2009	DBLP DOI BibTeX RDF
2	Shuo Shi, Hongli Tian, Yandong Zhai	Design of Intelligent Traffic Light Controller Based on VHDL.	WKDD	2009	DBLP DOI BibTeX RDF
2	Jian-Long Kuo	Intelligent Decoupled SAC-SVD Method in Color Space Transformation of Computer Vision.	IEA/AIE	2009	DBLP DOI BibTeX RDF	reconfigurable computing system (RCS), single assignment C (SAC), chromaticity coordinate, parallel computing, singular value decomposition (SVD), VHDL, data flow graph (DFG), color space, Decoupled
2	Stephen Wood, David H. Akehurst, O. Uzenkov, W. Gareth J. Howells, Klaus D. McDonald-Maier	A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil	Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	José A. Olivas, Roberto Sepúlveda, Oscar Montiel, Oscar Castillo	Methodology to Test and Validate a VHDL Inference Engine through the Xilinx System Generator.	Soft Computing for Hybrid Intelligent Systems	2008	DBLP DOI BibTeX RDF
2	Ismael Millán, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo	Design and Implementation of a Hybrid Fuzzy Controller Using VHDL.	Soft Computing for Hybrid Intelligent Systems	2008	DBLP DOI BibTeX RDF
2	Weiguang Sheng, Liyi Xiao, Zhigang Mao	An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.	DELTA	2008	DBLP DOI BibTeX RDF	simulated fault injection, reliability, VLSI, soft error, stratified sampling
2	Stephen Wood, David H. Akehurst, W. Gareth J. Howells, Klaus D. McDonald-Maier	Array OL Descriptions of Repetitive Structures in VHDL.	ECMDA-FA	2008	DBLP DOI BibTeX RDF
2	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
2	Günter Knittel, Stefanie Mayer, Christian Rothländer	Integrating Logic Analyzer Functionality into VHDL Designs.	ReConFig	2008	DBLP DOI BibTeX RDF	On-chip logic analyzer, FPGA, VHDL
2	In-Kwon Park, Jung-Hyun Kim, Kwang-Seok Hong	An implementation of an FPGA-based embedded gesture recognizer using a data glove.	ICUIMC	2008	DBLP DOI BibTeX RDF	FPGA, VHDL, gesture recognition
2	Angel Barriga Barros, Nashaat M. Hussein	A Fuzzy Thresholding Circuit for Image Segmentation.	KES	2008	DBLP DOI BibTeX RDF	Fuzzy Logic application, VHDL fuzzy system description, Image segmentation, image thresholding
2	Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar	A Compiler Intermediate Representation for Reconfigurable Fabrics.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	FPGA, VHDL, Configurable computing, Intermediate representation
2	Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi Gaydadjiev, Yi Lu 0004, Stamatis Vassiliadis	DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.	FPL	2007	DBLP DOI BibTeX RDF
2	Gildas Genest, Richard Chamberlain, Robin J. Bruce	Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C.	AHS	2007	DBLP DOI BibTeX RDF
2	Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo	A Methodology and Toolset to Enable SystemC and VHDL Co-simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Nikolay Kostadinov, Anelia Ivanova	A VHDL training model of a processor.	CompSysTech	2007	DBLP DOI BibTeX RDF	CPLD implementation, VHDL model, processor, instruction set
2	César A. M. Marcon, Sergio Johann Filho, Fabiano Hessel	A VHDL based approach for fast and accurate energy consumption estimations.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
2	Saeid Moslehpour, Chandrasekhar Puliroju, Christopher L. Spivey	Simulating VHDL in PSpice Software.	SCSS	2007	DBLP DOI BibTeX RDF
2	Maciej Brzozowski, Vyacheslav N. Yarmolik	Obfuscation as Intellectual Rights Protection in VHDL Language.	CISIM	2007	DBLP DOI BibTeX RDF
2	Juan Pablo Martinez Brito, Sergio Bampi	Design of a digital FM demodulator based on a 2nddegree order all-digital phase-locked loop.	SBCCI	2007	DBLP DOI BibTeX RDF	all-digital phase-locked loop (ADPLL), digital FM demodulator, frequency modulation (FM), FPGA, VHDL, software-defined radio (SDR), reconfigurable logic
2	B. Lorente, R. Aragonés, J. Oliver, C. Ferrer	Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development.	SCSC	2007	DBLP DOI BibTeX RDF	smart inertial sensors, UML, design methodology, behavioral modeling, distributed architecture, VHDL-AMS
2	David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda	Symbolic Model Checking of Analog/Mixed-Signal Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	analog/mixed-signal circuits, Boolean based symbolic model checking algorithm, VHDL-AMS description, labeled hybrid Petri nets, Boolean signals, temporal logic formulas, timed CTL, Boolean variables, Boolean function, binary decision diagram, hardware description language
2	Maher E. Rizkalla, Paul Salama, Mohamed El-Sharkawy, Modukuri Sushmitha	Hardware Implementation of Block-based Motion Estimation for Real Time Applications.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	fast search algorithms, exhaustive search algorithm, VHDL implementation, VLSI, motion estimation, finite state machine
2	Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein	From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.	FPL	2006	DBLP DOI BibTeX RDF
2	Oliver Pell, Wayne Luk	Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information.	FPL	2006	DBLP DOI BibTeX RDF
2	Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate	CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Felipe Machado, Teresa Riesgo, Yago Torroja	A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber	A Mixed Language Fault Simulation of VHDL and SystemC.	DSD	2006	DBLP DOI BibTeX RDF
2	Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio	VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák	Verifying VHDL Designs with Multiple Clocks in SMV.	FMICS/PDMC	2006	DBLP DOI BibTeX RDF
2	Johan Iskandar, John D. Zakis	VHDL Implementation of Neurone Networks Using a Simplified Action Potential Waveform.	CIMCA/IAWTIC	2006	DBLP DOI BibTeX RDF
2	Kaiping Zeng, Sorin A. Huss	Architecture refinements by code refactoring of behavioral VHDL-AMS models.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Betul Buyukkurt, Zhi Guo, Walid A. Najjar	Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
2	Marcelino Minero-Muñoz, Vicente Alarcón Aquino	A Hierarchical Approach for Modelling an MPLS Network Using VHDL.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
2	Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray	Hardware-based text-to-braille translator.	ASSETS	2006	DBLP DOI BibTeX RDF	braille translation, FPGAs, VHDL
2	Stephan Thesing	Modeling a system controller for timing analysis.	EMSOFT	2006	DBLP DOI BibTeX RDF	aiT, verification, static analysis, VHDL, timing analysis, WCET, worst-case execution time, avionics, peripherals
2	Tadayoshi Horita, Takurou Murata, Itsuo Takanami	A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.	DFT	2006	DBLP DOI BibTeX RDF	weight fault, neuron fault, fault tolerance, FPGA, VHDL, multilayer neural network
2	Kang Chul Kim, Chang-Gyoon Lim, Jae Hung Yoo, Seok Bung Han	Simulation Cost Reduction Strategies for Behavioral Model Verification in Bayesian Based Stopping Rule.	EUC	2006	DBLP DOI BibTeX RDF	behavioral VHDL model, semi-random variable, Verification, stopping rule, branch coverage
2	François Pêcheux, Christophe Lallement, Alain Vachoux	VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Kaiping Zeng, Sorin A. Huss	RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis.	ISVLSI	2005	DBLP DOI BibTeX RDF
2	Medard Rieder, Rico Steiner, Cathy Berthouzoz, Francois Corthay, Thomas Sterren	Synthesized UML, a Practical Approach to Map UML to VHDL.	RISE	2005	DBLP DOI BibTeX RDF