Search results for "VLIW"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
4	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	Performance evaluation, VLIW, ASIP, Clustered VLIW processors
4	Anup Gangwar, M. Balakrishnan, Anshul Kumar	Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	performance evaluation, VLIW, ASIP, clustered VLIW processors
4	Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. Tavares Fernandes	Datapath Design for a VLIW Video Signal Processor.	HPCA	1997	DBLP DOI BibTeX RDF	datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design
4	Soo-Mook Moon, Scott D. Carson	Generalized Multiway Branch Unit for VLIW Microprocessors.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	generalized multiway branching, VLIW microprocessor, condition tree, mirror normalization, VLIW compiler, Instruction-level parallelism, superscalar microprocessor
3	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	CSMT: Simultaneous Multithreading for Clustered VLIW Processors.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	clustered VLIW architectures, ILP, simultaneous multithreading, multithreaded processors, VLIW architectures
3	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
3	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	TACO	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
3	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Hybrid multithreading for VLIW processors.	CASES	2009	DBLP DOI BibTeX RDF	multithreading, clustered VLIW processors
3	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
3	Vincenzo Catania, Maurizio Palesi, Davide Patti	Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems.	TACO	2008	DBLP DOI BibTeX RDF	hyperblock formation, genetic algorithms, performances, statistical analysis, power, energy, design space exploration, multiobjective optimization, ILP, VLIW architectures
3	Jun Yan, Wei Zhang 0002	A time-predictable VLIW processor and its compiler support.	Real-Time Systems	2008	DBLP DOI BibTeX RDF	if-conversion, Compiler, VLIW, WCET analysis, Time-predictability
3	Wonchul Lee, Hyojin Choi, Wonyong Sung	Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	variable block size motion estimation, H.264/AVC encoder, VLIW (very long instruction word), SIMD (single instruction multiple data)
3	Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao	Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	register organization, VLIW, digital signal processor, micro-architecture, instruction encoding
3	Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee	Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	VLIW DSP processor, optimizing context switch overhead, microkernel design
3	Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee	Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	ping-pong register files, clustering, parallel processing, compiler, DSP, VLIW
3	Andrei Terechko, Henk Corporaal	Inter-cluster communication in VLIW architectures.	TACO	2007	DBLP DOI BibTeX RDF	intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment
3	Shu Xiao, Edmund Ming-Kit Lai	VLIW instruction scheduling for minimal power variation.	TACO	2007	DBLP DOI BibTeX RDF	power variation reduction, Instruction scheduling, VLIW processors
3	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
3	Milos Becvár, Stanislav Kahánek	VLIW-DLX simulator for educational purposes.	WCAE	2007	DBLP DOI BibTeX RDF	simulation, education, computer architecture, VLIW
3	Shan Yan, Bill Lin	Stream execution on wide-issue clustered VLIW architectures.	LCTES	2007	DBLP DOI BibTeX RDF	scheduling, compilers, VLIW processors, stream programming
3	Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee	Enabling compiler flow for embedded VLIW DSP processors with distributed register files.	LCTES	2007	DBLP DOI BibTeX RDF	distributed register files, embedded VLIW DSP compilers, software pipelining
3	Weifeng Xu, Russell Tessier	Tetris: a new register pressure control technique for VLIW processors.	LCTES	2007	DBLP DOI BibTeX RDF	register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
3	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
3	Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Reducing dynamic and leakage energy in VLIW architectures.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF	dynamic energy, schedule slacks, compiler, VLIW architecture, leakage energy
3	Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Loop scheduling with timing and switching-activity minimization for VLIW DSP.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction bus optimization, low-power optimization, compilers, software pipelining, VLIW, retiming, instruction scheduling, loops
3	Rahul Nagpal, Y. N. Srikant	Compiler-assisted leakage energy optimization for clustered VLIW architectures.	EMSOFT	2006	DBLP DOI BibTeX RDF	scheduling, leakage energy, energy-aware scheduling, clustered VLIW processors
3	Won So, Alexander G. Dean	Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP.	CASES	2006	DBLP DOI BibTeX RDF	TI C6000, static profitability estimation, DSP, software pipelining, VLIW, iterative compilation, software thread integration
3	Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed thermal management for VLIW functional units.	LCTES	2006	DBLP DOI BibTeX RDF	VLIW, thermal, IPC
3	Emre Özer, Thomas M. Conte	High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	Multithreaded processors, VLIW architectures, modeling of computer architecture
3	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
3	Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man	Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	low-power-dissipation, performance, memory, VLIW processors, multi-media, code transformations, subword parallelism, system level
3	Antonio Carlos Schneider Beck, Luigi Carro	A VLIW low power Java processor for embedded applications.	SBCCI	2004	DBLP DOI BibTeX RDF	Java, power consumption, VLIW
3	Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon	Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low-power design, branch prediction, VLIW processors
3	Montserrat Ros, Peter Sutton	A hamming distance based VLIW/EPIC code compression technique.	CASES	2004	DBLP DOI BibTeX RDF	VLIW, hamming distance, code compression
3	Rahul Nagpal, Y. N. Srikant	Integrated temporal and spatial scheduling for extended operand clustered VLIW processors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	spatial scheduling, temporal scheduling, clustered VLIW processors
3	Binu K. Mathew, Al Davis	A loop accelerator for low power embedded VLIW processors.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, VLIW
3	Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai	Compiler optimization on VLIW instruction scheduling for low power.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers
3	Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon	Branch prediction techniques for low-power VLIW processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	low-power design, branch prediction, VLIW processors
3	Andrei Terechko, Erwan Le Thenaff, Henk Corporaal	Cluster assignment of global values for clustered VLIW processors.	CASES	2003	DBLP DOI BibTeX RDF	compiler, register allocation, VLIW, instruction scheduler, ILP, cluster assignment
3	Osvaldo Colavin, Davide Rizzo	A scalable wide-issue clustered VLIW with a reconfigurable interconnect.	CASES	2003	DBLP DOI BibTeX RDF	clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT
3	Montserrat Ros, Peter Sutton	Compiler optimization and ordering effects on VLIW code compression.	CASES	2003	DBLP DOI BibTeX RDF	compiler optimizations, VLIW, code compression
3	Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon	A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.	DATE	2003	DBLP DOI BibTeX RDF	Data compression algorithms, system-level energy optimization, VLIW embedded processors
3	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Adapting instruction level parallelism for optimizing leakage in VLIW architectures.	LCTES	2003	DBLP DOI BibTeX RDF	power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units
3	Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana	Cluster assignment for high-performance embedded VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Operation binding, clustered VLIW datapaths, embedded systems, partitioning, embedded processors
3	V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	VLIW processor test, test-time analysis, Design for Testability (DfT), test synthesis
3	Sunghyun Jee, Kannappan Palaniappan	Dynamically Scheduling VLIW Instructions with Dependency Information.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	DISVLIW, VLIW, Dynamic Scheduling, Processor Architecture, ILP
3	Sunghyun Jee, Kannappan Palaniappan	Performance evaluation for a compressed-VLIW processor.	SAC	2002	DBLP DOI BibTeX RDF	CVLIW processor, individual instruction scheduling, VLIW, ILP
3	Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon	Energy estimation and optimization of embedded VLIW processors based on instruction clustering.	DAC	2002	DBLP DOI BibTeX RDF	power estimation, vliw architectures
3	Carles Rodoreda Sala, Natalino G. Busá	A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor.	ISSS	2002	DBLP DOI BibTeX RDF	VLIW processors, reconfigurable logic, architectural synthesis
3	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
3	Enric Gibert, F. Jesús Sánchez, Antonio González	An interleaved cache clustered VLIW processor.	ICS	2002	DBLP DOI BibTeX RDF	attraction buffers, modulo scheduling, VLIW processors, distributed cache, clustered microarchitectures
3	Yi Qian, Steve Carr, Philip H. Sweany	Loop fusion for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	clustered VLIW architectures, loop fusion
3	Xiushan Feng, Alan J. Hu	Automatic formal verification for scheduled VLIW code.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	theory of equality with uninterpreted functions, formal verification, DSP, VLIW, symbolic execution
3	Shyh-Kwei Chen, W. Kent Fuchs	Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry
3	David López, Josep Llosa, Mateo Valero, Eduard Ayguadé	Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	numerical applications, performance/cost trade-off, instruction level parallelism, software pipelining, VLIW processors
3	Cristiana Bolchini, Fabio Salice	A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Software code scheduling, VLIW processors, Hardware fault detection
3	Elana D. Granston, Eric Stotzer, Joe Zbiciak	Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture.	LCTES/OM	2001	DBLP DOI BibTeX RDF	WHILE loops, software pipelining, digital signal processors, VLIW architectures
3	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors.	CODES	2001	DBLP DOI BibTeX RDF	embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors
3	Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau	Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	code size minimization, custom templates, instruction format design, noop compression, retargetable assembly, VLIW, design automation, EPIC
3	Thomas M. Conte, Sumedh W. Sathaye	Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	instruction-set encoding, list encoding, VLIW, Microarchitecture, processor architecture, instruction cache
3	Alberto Ferreira de Souza, Peter Rounce	On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	DTSVLIW, VLIW, Instruction scheduling
3	Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte	A Fast Interrupt Handling Scheme for VLIW Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue
3	Zhao Wu, Wayne Wolf	Design Study of Shared Memory in VLIW Video Signal Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	VSP, stride prediction table, cache, shared memory, VLIW, trace-driven simulation, memory system, stream buffer, multi-cluster
3	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye	Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.	MICRO	1996	DBLP BibTeX RDF	TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures
3	Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia	A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures.	MICRO	1996	DBLP BibTeX RDF	LRU replacement, disk caching scheme, dynamic rescheduling, first-time page faults, high-overhead programs, low overhead object code compatibility, overhead-based replacement, page replacement policies, persistent rescheduled-page cache, run-time software rescheduling, simulations, cache storage, VLIW architectures, program executions, operating system support, program performance
3	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Scheduling of conditional branches using SSA form for superscalar/VLIW processors. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
3	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Eliminating Conditional Branches for Enhancing Instruction Level Parallelism in VLIW Compiler.	ISPAN	1996	DBLP DOI BibTeX RDF	Compiler, Instruction Level Parallelism, VLIW, Superscalar, Conditional Branches
3	Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya	Industrial experience using rule-driven retargetable code generation for multimedia applications.	ISSS	1995	DBLP DOI BibTeX RDF	VideoPhone codec controller, audio telecommunications, dedicated compiler availability, high-fidelity audio, optimization abilities, rule-driven retargetable code generation, video telecommunications, knowledge based systems, computer architecture, multiprocessing systems, multimedia systems, application specific integrated circuits, multimedia applications, application-specific instruction set processors, instruction sets, telecommunication computing, codecs, VLIW processor, VLIW architecture, transformation rules, controller architecture, optimising compilers, industrial experience, videotelephony, target architecture, MPEG audio
3	Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv	VLIW Compilation Techniques in a Superscalar Environment.	PLDI	1994	DBLP DOI BibTeX RDF	profiling directed feedback, compiler optimizations, software pipelining, VLIW, superscalars, global scheduling, IBM RS/6000
3	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
2	Thorsten Jungeblut, Gregor Sievers, Mario Porrmann, Ulrich Rückert	Design Space Exploration for Memory Subsystems of VLIW Architectures.	NAS	2010	DBLP DOI BibTeX RDF	CoreVA, Cache, Design Space Exploration, VLIW, Memory Subsystem
2	Talal Bonny, Jörg Henkel	LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors.	DAC	2009	DBLP DOI BibTeX RDF	embedded systems, code compression, Huffman coding
2	Yangyang Pan, Tong Zhang	Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking.	ASAP	2009	DBLP DOI BibTeX RDF
2	Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby	On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors.	HPCC	2009	DBLP DOI BibTeX RDF
2	Wen-Wen Hsieh, TingTing Hwang	Thermal-aware post compilation for VLIW architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Yingchao Zhao, Chun Jason Xue, Minming Li, Bessie C. Hu	Energy-aware register file re-partitioning for clustered VLIW architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Dimitris Theodoropoulos, Alexandros Siskos, Dionisios N. Pnevmatikatos	CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers.	ARC	2009	DBLP DOI BibTeX RDF	Cryptography, VLIW, reconfigurable processors
2	Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala	Programmable and Scalable Architecture for Graphics Processing Units.	SAMOS	2009	DBLP DOI BibTeX RDF	TTA, GPU, GPGPU, VLIW, OpenGL, GLSL, LLVM
2	Shu Xiao, Edmund Ming-Kit Lai	A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors.	IEEE Transactions on Signal Processing	2008	DBLP DOI BibTeX RDF
2	Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen	An Online Control Flow Check for VLIW Processor.	PRDC	2008	DBLP DOI BibTeX RDF
2	Markus Koester, Wayne Luk, Geoffrey Brown	A hardware compilation flow for instance-specific VLIW cores.	FPL	2008	DBLP DOI BibTeX RDF
2	Benoît Dupont de Dinechin	Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors.	Euro-Par	2008	DBLP DOI BibTeX RDF
2	Mattias V. Eriksson, Oskar Skoog, Christoph W. Kessler	Optimal vs. heuristic integrated code generation for clustered VLIW architectures.	SCOPES	2008	DBLP DOI BibTeX RDF
2	Meng Wang, Zili Shao, Hui Liu, Chun Jason Xue	Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.	DIPES	2008	DBLP DOI BibTeX RDF
2	Chun-Nan Liu, Jui Hong Hung, Tsung-Han Tsai	Optimization techniques of AAC decoder on PACDSP VLIW processor.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal	Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.	HiPEAC	2008	DBLP DOI BibTeX RDF
2	Talal Bonny, Jörg Henkel	FBT: filled buffer technique to reduce code size for VLIW processors.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Ya-shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao	Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques.	DAC	2008	DBLP DOI BibTeX RDF	subgraph covering, VLIW, ASIPs, extensible processors
2	Peter Rounce, Alberto Ferreira de Souza	Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Simultaneous multi-threading, Wide issue architectures, VLIW, Dynamic instruction scheduling
2	Jonah Probell	Architecture Considerations for Multi-Format Programmable Video Processors.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	software programmable processor, hardwired processor, data tiling, SIMD, VLIW, processor architecture, multiprocessing
2	Tsung-Han Tsai, Chun-Nan Liu	A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Prefix grouping, VLIW DSP processor, Multimedia, Parallel processing, Huffman coding
2	Ihor O. Kirenko, René J. van der Vleuten, Ling Shao	Optimizing Scalable Video Compression for Efficient Implementation on a VLIW Media Processor.	IEEE Transactions on Multimedia	2007	DBLP DOI BibTeX RDF
2	Chang Hong Lin, Yuan Xie, Wayne Wolf	Code Compression for VLIW Embedded Systems Using a Self-Generating Table.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Yuan Xie, Wayne Wolf, Haris Lekatsas	Code Decompression Unit Design for VLIW Embedded Processors.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Shuming Chen, Xiao Hu, Biwei Liu, Jihua Chen	An On-Line Control Flow Checking Method for VLIW Processor.	PRDC	2007	DBLP DOI BibTeX RDF
2	Rahul Nagpal, Y. N. Srikant	Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures.	HiPC	2007	DBLP DOI BibTeX RDF
2	Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
2	Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli	Heterogeneous Clustered VLIW Microarchitectures.	CGO	2007	DBLP DOI BibTeX RDF
2	Min Li, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor	A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture.	SiPS	2007	DBLP DOI BibTeX RDF