Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri	A VLSI chip for image compression using variable block size segmentation. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	variable block size segmentation, VBSS scheme, variable size blocks, redundancy features, maximum compression, nearest neighbor communication, CMOS VLSI chip, image characteristics extraction subsystem, Cadence design tools, VLSI, parallelism, pipelining, image compression, VLSI architecture, VLSI implementation, lossless image compression, VLSI chip, coding techniques
8	Mario Kovac, N. Ranganathan	JAGUAR: a high speed VLSI chip for JPEG image compression standard.	VLSI Design	1995	DBLP DOI BibTeX RDF	JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz
7	Jens Lienig	Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach.	VLSI Design	1997	DBLP DOI BibTeX RDF	minimized crosstalk, interconnection routing, interconnection crosstalk, VLSI channel routing, VLSI switchbox routing, distributed workstation network, VLSI, VLSI design, parallel genetic algorithm
7	Prathima Agrawal, B. Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
7	John A. Chandy, Prithviraj Banerjee	Parallel simulated annealing strategies for VLSI cell placement.	VLSI Design	1996	DBLP DOI BibTeX RDF	parallel simulated annealing strategies, VLSI cell placement, cell placement annealing, multiple Markov chains, parallel moves approach, parallel algorithms, VLSI, simulated annealing, Markov processes, VLSI design, circuit layout CAD, integrated circuit layout, speculative computation, standard cell placement
7	Si-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar	Routing using implicit connection graphs [VLSI design.	VLSI Design	1996	DBLP DOI BibTeX RDF	implicit connection graphs, shortest path related problems, minimum spanning tree problem, sparse strong connection graph, large VLSI design applications, VLSI, graph theory, search problems, circuit layout CAD, VLSI layout, integrated circuit layout, obstacles, search behavior
7	Wallace B. Leigh	A personal computer based VLSI design curriculum.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design curriculum, teaching institutions, capstone VLSI course, analog design course, digital design synthesis course, teaching curriculum, VLSI, design methodology, integrated circuit design, circuit CAD, personal computers, computer aided instruction, microcomputer applications, electronic engineering education
7	Luca Penzo, Donatella Sciuto, Cristina Silvano	VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes.	VLSI Design	1995	DBLP DOI BibTeX RDF	odd-weight-column byte error detection, SEC-DED codes, single error correction, double error detection, single byte error detection, SEC-DED-SBD codes, high performances VLSI implementations, high speed encoding/decoding circuits, parallel data manipulation, VHSIC Hardware Description Language, VHDL description, parallel processing, VLSI, software tool, error correction codes, application specific integrated circuits, logic CAD, decoding, VLSI design, error detection codes, hardware description languages, integrated logic circuits, digital integrated circuits
7	Hossein Sahabi, Anup Basu, Mark Fiala	VLSI implementation of variable resolution image compression.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable resolution image compression, bandwith requirements, telepresence system, teleconferencing systems, encoding/decoding subsystem, SBus interface, VLSI codec chip, real time compression, real time decompression, video rates, output image quality, 1024 pixel, 1048576 pixel, real-time systems, VLSI, data compression, image coding, teleconferencing, image resolution, video signal processing, digital signal processing chips, VLSI implementation, codecs, video codecs
6	David Hertweck, Mihaela Nica, Sang-Eon Park, Carla N. Purdy	Standard Data Representations for VLSI Algorithm Development.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	VLSi design, benchmarking, graph partitioning, VLSI algorithms
6	Ron Lin	Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes.	VLSI Design	1997	DBLP DOI BibTeX RDF	shift switching, asynchronous VLSI comparator, precharged CMOS domino logic, VLSI, semaphore
6	Kamran Eshraghian	Opto-VLSI Systems for Multimedia Computing.	VLSI Design	1997	DBLP DOI BibTeX RDF	opto-VLSI systems, online compression, online coding, VLSI, multimedia computing, processing capability, image capture
6	S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	programmable cellular automata, polynomial algebraic tools, faulty signatures, multiple attractor, fault dictionary size, cascadable structure, VLSI, fault diagnosis, fault diagnosis, logic testing, partitions, cellular automata, integrated circuit testing, automatic testing, VLSI circuits, logic partitioning, signature analyzer
6	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
6	Sunil R. Das, N. Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
6	Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya	Geometric bipartitioning problem and its applications to VLSI.	VLSI Design	1996	DBLP DOI BibTeX RDF	geometric bipartitioning problem, layout design, rectilinear modules, staircase, monotone increasing, classical graph bisection problem, weighted permutation graph, integer edge weights, designated nodes, absolute value, edge weights, routing, computational complexity, VLSI, VLSI, graph theory, NP-complete, branch-and-bound, floorplan, heuristic algorithm, search problems, geometry, network routing, circuit layout CAD, hierarchical decomposition
6	N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar	A VLSI array architecture with dynamic frequency clocking. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	VLSI array architecture, dynamic frequency clocking, linear VLSI array processor, DFLAP, power requirements, image processing, VLSI, throughput
6	Robert Pearson	Linking fabrication and parametric testing to VLSI design courses.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design courses, simulation model parameters, VLSI, integrated circuit testing, integrated circuit design, integrated circuit modelling, educational courses, device models, parametric testing, electronic engineering education
6	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
6	Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen	An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching network fault diagnosis, reconfigurable VLSI/WSI array processors, switching network defects, killing error, testing circuit overhead, diagnosis time, mesh array, VLSI, parallel architectures, fault diagnosis, reconfigurable architectures, multiple faults, switching networks, wafer-scale integration, testing quality
6	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
6	S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy	Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements.	VLSI Design	1995	DBLP DOI BibTeX RDF	very high speed integrated circuits, transmission line theory, integrated circuit packaging, transmission line model parameters, very high speed VLSI interconnects, higher order isoparametric elements, 2D interconnect/dielectric packaging structures, quadrilateral infinite elements, signal conductor boundaries, sharp corners, finite element method, finite element analysis, computation time, multichip modules, multichip modules, FEM, MCM, integrated circuit interconnections, VLSI interconnects
6	Giuseppe Ascia, Vincenzo Catania	Design of a VLSI parallel processor for fuzzy computing.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI parallel processor, fuzzy computing, /spl alpha/-level sets theory, memory resources, processing units, 50 MHz, scalability, VLSI, parallelism, fuzzy logic, parallel architectures, inference mechanisms, fuzzy set theory, integrated circuit design, microprocessor chips, membership functions, fuzzy inferences, clock frequency, 8 bit
6	Anoop Singhal, Chi-Yuan Lo	Object oriented data modeling for VLSI/CAD.	VLSI Design	1995	DBLP DOI BibTeX RDF	design data manager, integrated CAD system, modular program architecture, VLSI, object-oriented methods, integrated circuit design, circuit CAD, object oriented data modeling, VLSI CAD
6	Anand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu	Extending VLSI design with higher-order logic. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	Cambridge Higher-Order Logic theorem-prover, microprogram sequencer, Am2910, VLSI, formal verification, formal verification, logic testing, theorem proving, logic design, logic CAD, VLSI design, higher-order logic, theorem-prover, design environment, instruction-set architecture, VLSI CAD
6	N. Ranganathan, K. B. Doreswamy	A systolic algorithm and architecture for image thinning.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
6	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
5	Yang Sun, Joseph R. Cavallaro	High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	mimo detection, VLSI architecture, ASIC design
5	Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto	A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fast intra prediction mode decision, H.264, VLSI architecture
5	Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi	Equidistance routing in high-speed VLSI layout design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	box routing, equidistance routing, rectilinear route, slant symmetric grid, dynamic programming, VLSI system, channel routing
5	Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin	A memory aware behavioral synthesis tool for real-time VLSI circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	memory aware, behavioral synthesis, VLSI circuits
5	Menahem Lowy, Neal Butler, Rosanne Tinkler	Low power VLSI sequential circuit architecture using critical race control.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	critical races, low-power VLSI circuits, asynchronous circuits
5	Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan	VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images.	VLSI Design	2003	DBLP DOI BibTeX RDF	Image Processing, VLSI, Watermarking, ASIC design
5	Wu Jigang, Thambipillai Srikanthan	A Run-time Reconfiguration Algorithm for VLSI Arrays.	VLSI Design	2003	DBLP DOI BibTeX RDF	Degradable VLSI/WSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm
5	Falah R. Awwad, Mohamed Nekili	Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	parallel regeneration, VLSI, repeater, RLC interconnect
5	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
5	Adger E. Harvin III, José G. Delgado-Frias	A Dictionary Machine Emulation on a VLSI Computing Tree System.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	tree architectures, VLSI, data structure, pipeline computing, bit-serial, Dictionary machines
5	Anthony D. Johnson	Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	vertical constraints, VLSI, theory, local optimality, Channel Routing
5	José G. Delgado-Frias, Richard Diaz	A VLSI Self-Compacting Buffer for DAMQ Communication Switches.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	dynamically allocated multi-queue, Communication buffer management, VLSI, Communication Switches
5	Gert Cauwenberghs	Design and VLSI Implementation of an Adaptive Delta-Sigma Modulator.	VLSI Design	1998	DBLP DOI BibTeX RDF	neural networks, reinforcement learning, analog VLSI, delta-sigma modulation, analog-to-digital conversion
5	S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, M. S. Diamondstein	VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.	VLSI Design	1998	DBLP DOI BibTeX RDF	Fast counter, VLSI, Testability
5	Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele	A flexible VLSI architecture for variable block size segment matching with luminance correction.	ASAP	1997	DBLP DOI BibTeX RDF	flexible VLSI architecture, variable block size segment matching, luminance correction, segment matching VLSI architecture, evolving motion estimation algorithms, preprocessing unit, halfpel interpolation, pixel decimation, VHDL synthesis, VLSI, CMOS technology, motion vectors, RAM, block matching algorithms, video coding standards
5	Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada	A practical approach to instruction-based test generation for functional modules of VLSI processors.	VTS	1997	DBLP DOI BibTeX RDF	VLSI processors, instruction-based test generation, functional test pattern generation, gate level faults, constrained test generation, ALU oriented test pattern generation system, VLSI, functional modules, ALPS
5	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal	An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.	VLSI Design	1997	DBLP DOI BibTeX RDF	three-layer restricted dogleg routing model, nontrivial lower bound, channel routing problem, two-layer Manhattan routing model, three-layer no-dogleg HVH routing model, two-layer restricted dogleg routing model, vertical constraint graph, VLSI, polynomial time algorithm, VLSI design
5	Minesh I. Patel, N. Ranganathan	A VLSI System Architecture For Real-Time Intelligent Decision Making.	ASAP	1996	DBLP DOI BibTeX RDF	VLSI system architecture, real-time intelligent decision making, backpropagation based neural network, rule based fuzzy expert system, real-time decision, CMOS VLSI chip, real-time systems, VLSI, expert systems, systolic arrays, neural nets, backpropagation, CMOS integrated circuits, adaptive learning, linear systolic arrays
5	S. Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri	A VLSI architecture for cellular automata based parallel data compression.	VLSI Design	1996	DBLP DOI BibTeX RDF	parallel data compression, nongroup CA, VLSI, parallel architectures, data compression, cellular automata, cellular automata, VLSI architecture, state transition
5	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
5	Chuan-Yu Wang, Kaushik Roy	Maximum power estimation for CMOS circuits using deterministic and statistic approaches.	VLSI Design	1996	DBLP DOI BibTeX RDF	maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach
5	S. Sundaram, Lalit M. Patnaik	Distributed logic simulation: time-first evaluation vs. event driven algorithms.	VLSI Design	1996	DBLP DOI BibTeX RDF	distributed logic simulation, time-first evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation
5	Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst	Silicon VLSI processing architectures incorporating integrated optoelectronic devices.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si
5	Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth	Analog VLSI circuits for manufacturing inspection.	ARVLSI	1995	DBLP DOI BibTeX RDF	analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits
5	Anthony D. Johnson	On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally optimal breaking strategy, nondisjoint cyclic vertical constraints, VLSI channel routing, vertical constraint graph, nondisjoint circuits, common vertex, common path, channel router heuristics, automatic routers, interactive routers, VLSI, graph theory, parallel architectures, network routing, circuit layout CAD, integrated circuit layout
5	Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barros, Raúl Jiménez, José L. Huertas	New CMOS VLSI linear self-timed architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
5	Bjørn Olstad, E. Steen, Arne Halaas	Image filtering techniques and VLSI architectures for efficient data extraction in shell rendering. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	image filtering techniques, shell rendering, interactive data reduction, real-time data reduction, PCI based search engine, full custom VLSI chip, opacity assignment, multi-spectral voxel data, interactive inspection procedures, 3D imagery, 3D ultrasonics, 3D MRI studies, classification, VLSI, feature extraction, volume rendering, image classification, application specific integrated circuits, medical image processing, search problems, VLSI architectures, filtering theory, data reduction, digital signal processing chips, data extraction, rendering (computer graphics), biomedical NMR, image preprocessing, biomedical ultrasonics
5	Zhan Chen, Israel Koren	Techniques for Yield Enhancement of VLSI Adders.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI yield, VLSI adder, defect tolerance, VLSI layout
5	P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	VLSI floorplan generation and area optimization using AND-OR graph search.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph
5	Vincenzo Catania, Marco Russo	Analog gates for a VLSI fuzzy processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI fuzzy processor, synchronous fuzzy circuits, high noise immunity, fuzzy gates, VLSI, fuzzy logic, CMOS logic circuits, CMOS technology, logic gates, analogue processing circuits
5	Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak	An improved output compaction technique for built-in self-test in VLSI circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
5	Meenakshisundaram Gopi, Swami Manohar	A VLSI architecture for the computation of NURBS patches.	VLSI Design	1995	DBLP DOI BibTeX RDF	NURBS patches, nonuniform rational B-spline, interactive modeling session, patch generation, complete hardware solution, VLSI, computational geometry, parallel architectures, computer graphics, geometric modeling, VLSI architecture, splines (mathematics), B-spline curves
5	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
5	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
5	Nikolaos G. Bourbakis, Mohammad Mortazavi	An efficient building block layout methodology for compact placement.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing
5	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
5	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
5	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, N. Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division
5	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
5	S. C. Prasad, Kaushik Roy	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
5	Luis A. Montalvo, Alain Guyot	Svoboda-Tung division with no compensation.	VLSI Design	1995	DBLP DOI BibTeX RDF	Svoboda-Tung division, radix-b division algorithm, iteration overflow, most significant digits, radix-b algorithm, IEEE normalised divisor, pre-scaling technique, stepwise approximation, VLSI, iterative methods, digital arithmetic, VLSI implementation, prescalers, dividing circuits
5	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
5	Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri	Board level fault diagnosis using cellular automata array.	VLSI Design	1995	DBLP DOI BibTeX RDF	board level fault diagnosis, cellular automata array, output responses, encoding strategy, byte error correcting code, encoded symbols, decoding structure, VLSI, fault diagnosis, logic testing, cellular automata, error correction codes, VLSI implementation, test vectors
5	Ali Skaf, Alain Guyot	SAGA: the first general-purpose on-line arithmetic co-processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	general-purpose co-processor, online arithmetic coprocessor, VLSI realisation, BKM algorithm, complex logarithm function, complex exponential function, VLSI, arithmetic, coprocessors, CMOS digital integrated circuits, redundant number systems, CMOS IC, SAGA
5	Hartmut Schmeck, Heiko Schröder	Dictionary Machines for Different Models of VLSI.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	VLSI hardware models, Dictionary machines. are taken as an example to demonstrate the implications the choice of the VLSI hardware model has on the design and analysis of algorithms and special purpose architectures, A systolic search tree and a two-dimensional systolic array are used to implement the dictionary machine, If the wire lengths only affect the area, the systolic search tree suggests itself as an efficient realization of a dictionary machine having constant period, linear areS and logarithmic execution t, Algorithms for VLSI, systolic search tree, systolic array, VLSI complexity, dictionary machine
4	Pey-Chang Kent Lin, Sunil P. Khatri	VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	NLFSR, stream cipher, pseudo-random sequence
4	Yongji Jiang, Garrett S. Rose	A dual-MOSFET equivalent resistor thermal sensor.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	integrated circuits, dynamic thermal management, vlsi, temperature sensors
4	J. V. R. Ravindra, M. B. Srinivas	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	krylov subspace techniques, monte-carlo simulation, model order reduction, rlc
4	Pradeep Fernando, Srinivas Katkoori	An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.	VLSI Design	2008	DBLP DOI BibTeX RDF
4	Ivan D. Castellanos, James E. Stine	Compressor trees for decimal partial product reduction.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	VLSI, decimal arithmetic
4	Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan	Single Error Correcting Finite Field Multipliers Over GF(2m).	VLSI Design	2008	DBLP DOI BibTeX RDF	Galois Field Multiplier, VLSI, Cryptography, Error Correcting Codes
4	Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri	High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	code construction, fully-parallel VLSI implementation, network of PLAs, iterative decoding, low-density parity-check codes
4	Dimitrios N. Serpanos, Wayne Wolf	VLSI models of network-on-chip interconnect.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
4	Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack	NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	modeling, crosstalk, static timing analysis
4	M. Watanabe, F. Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
4	Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara	VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition.	VLSI Design	2007	DBLP DOI BibTeX RDF
4	Qianneng Zhou, Fengchang Lai, Yongsheng Wang	On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI Chips.	VLSI Design	2007	DBLP DOI BibTeX RDF
4	Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary	A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes.	VLSI Design	2007	DBLP DOI BibTeX RDF
4	C. Hess, Markus Wenk, Andreas Burg, Peter Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner	Reduced-complexity mimo detector with close-to ml error rate performance.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FSD, VLSI, MIMO, sphere decoding
4	Zhan Guo, Peter Nilsson	A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	square root algorithm, VLSI, wireless LAN, ASIC, MIMO, fixed-point, 3G, HSDPA, CORDIC, BLAST
4	Se Hun Kim, Vincent John Mooney	Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
4	Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan	Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.	VLSI Design	2006	DBLP DOI BibTeX RDF
4	Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty	A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm.	VLSI Design	2006	DBLP DOI BibTeX RDF
4	Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin	Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.	VLSI Design	2006	DBLP DOI BibTeX RDF
4	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters.	VLSI Design	2006	DBLP DOI BibTeX RDF
4	Wonyong Sung, Youngho Ahn, Eunjoo Hwang	VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	adaptive equalizer, HDTV receiver, VSB modulation, VLSI implementation
4	Fan Xu, Guichang Zhong, Alan N. Willson Jr.	Analysis and VLSI Realization of a Blind Beamforming Algorithm.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	blind beamforming, VLSI architecture, eigenvector, multi-processor, power method
4	Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak	Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	Reed-Solomon decoders, Sudan's algorithm, Guruswami-Sudan algorithm, Koetter-Vardy algorithm, Hasse derivative, VLSI architectures, list decoding, polynomial interpolation, soft-decision decoding
4	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen	VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	shape-adaptive, boundary extension, discrete wavelet transform, VLSI architecture
4	Lin Yuan, Gang Qu, Ankur Srivastava	VLSI CAD tool protection by birthmarking design solutions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	birthmarking, CAD, protection, intellectual property
4	Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi	Enhancing error resilience for reliable compression of VLSI test data.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	reliable compression, ATE, test data compression
4	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
4	Parthasarathi Dasgupta	Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions.	VLSI Design	2005	DBLP DOI BibTeX RDF