Search results for "VLSI Design"

Hits ?▲	Authors	Title	Venue	Year	Link
1	A. Kishore Kumar, D. Somasundareswari, V. Duraisamy, T. Shunbaga Pradeepa	Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Yu-Cheng Fan, Yi-Feng Chiang	Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Mauro Olivieri, Antonio Mastrandrea	A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Shadi Traboulsi, Valerio Frascolla, Nils Pohl, Josef Hausner, Attila Bilgic	Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Hiroki Iwaizumi, Shingo Yoshizawa, Yoshikazu Miyanaga	A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Kamran Rahmani, Prabhat Mishra	Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan	Localized Heating for Building Energy Efficiency.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Rashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta, Pat Bosshart	A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Subhankar Mukherjee	Formal Verification of Hardware / Software Power Management Strategies.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Saptarshi Roy, Amit Patra, Partha Pratim Chakrabarti, Purnendu Sinha, Dipankar Das 0002	Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal	Verification of KPN Level Transformations.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Rajath Vasudevamurthy, Bharadwaj Amrutur	Multiphase Technique to Speed-up Delay Measurement via Sub-sampling.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Bipin Rajendran	Embedded tutorial - Can silicon machines match the efficiency of the human brain?	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Ankush Jain, Ram Gopal	Design and Simulation of Structurally Decoupled 4-DOF MEMS Vibratory Gyroscope.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Sanku Mukherjee, Srinivasaraman Chandrasekaran, Ganapathy Subramanyan E. K., Arul Sendhil	At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Liang Tang, Jude Angelo Ambrose, Sri Parameswaran	MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi	Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Kanad Basu, Prabhat Mishra, Priyadarsan Patra	Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Amiya Prasad Behera, Subhasis Sasmal, Prajit Nandi	A Wide Range CMOS VCO for PLL Applications.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Sparsh Mittal, Zhao Zhang, Yanan Cao	CASHIER: A Cache Energy Saving Technique for QoS Systems.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	P. Deepa, C. Vasanthanayaki	VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Rahul Shrestha, Roy Paily	Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Pavlos M. Mattheakis, Christos P. Sotiriou	Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha	PODIA: Power Optimization through Differential Imbalanced Amplifier.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Sabyasachi Deyati, Aritra Banerjee, Barry John Muldrey, Abhijit Chatterjee	VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Maryamsadat Hashemian, Swarup Bhunia	Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Raka Sardar, Ratna Mondal, Tuhina Samanta	Geometry Independent Wirelength Estimation Method in VLSI Routing.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham	Dynamic Trace Signal Selection for Post-Silicon Validation.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury	Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran	A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang	On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Md. Shamsujjoha, Hafiz Md. Hasan Babu	A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Anvesha Amaravati, Maryam Shojaei Baghini	A Sub-1V 32nA Process, Voltage and Temperature Invariant Voltage Reference Circuit.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia	Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Yang Yang, Niraj K. Jha	Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Thannirmalai Somu Muthukaruppan, Tulika Mitra	Lifetime Reliability Aware Architectural Adaptation.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal	Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Cheekala Lovaraju, Ashis Maity, Amit Patra	A Capacitor-less Low Drop-out (LDO) Regulator with Improved Transient Response for System-on-Chip Applications.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Rajat Chauhan, Manigandan Selvam	Input Referred Offset Reduction in Very High Speed Differential Receivers.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Ruchir Puri	Keynote talk: Opportunities and challenges for high performance microprocessor designs and design automation.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Neeraj Mishra, Niraj Jha, Santanu Kapat, Amit Patra	Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, D. Lea, D. Sciacca	Hardware-corroborated Variability-Aware SRAM Methodology.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha	Energy-efficient and Secure Sensor Data Transmission Using Encompression.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal	Tutorial T10: Post - Silicon Validation, Debug and Diagnosis.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Debashis Banerjee, Aritra Banerjee, Abhijit Chatterjee	Adaptive RF Front-end Design via Self-discovery: Using Real-time Data to Optimize Adaptation Control.	VLSI Design	2013	DBLP DOI BibTeX RDF
1		26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013	VLSI Design	2013	DBLP BibTeX RDF
1	Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu	Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Surhud Khare, Shailendra Jain	Prospects of Near-Threshold Voltage Design for Green Computing.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Prashant Dubey, Rashmi Agarwal	38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Jim Monthie, Vineet Sreekumar, Ranjit Yashwante	Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory Interfaces.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi	Embedded tutorial - Emerging memory technologies: What it means for computer system designers.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya	Microelectromechanical Longitudinal Resonator for Frequency Reference Applications.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao	Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha	Emerging Frontiers in Embedded Security.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar	Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Sukeshwar Kannan, Bruce C. Kim, Anurag Gupta, Friedrich Taenzler, Richard Antley, Ken Moushegian	Physics Based Fault Models for Testing High-Voltage LDMOS.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Vinay M. M., Roy Paily, Anil Mahanta	Gain, NF and IIP3 Budgeting of LTE Receiver Front End.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Sanku Mukherjee, M. Thrivikraman M., Anil K. Goyal, Arul Sendhil	A Novel Scheme to Reset through Clock.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	K. Naveen, Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma	A Feed-Forward Equalizer for Capacitively Coupled On-Chip Interconnect.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan	Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Ankit Kagliwal, Shankar Balachandran	Measuring Area-Complexity Using Boolean Difference.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Hyuksu Son, Woo Young Kim, Joo Young Jang, Hae Jin Lee, Inn Yeal Oh, Chul Soon Park	A Fully Integrated CMOS Class-E Power Amplifier for Reconfigurable Transmitters with WCDMA/WiMAX Applications.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Mingsong Chen, Prabhat Mishra	Assertion-Based Functional Consistency Checking between TLM and RTL Models.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Abhirup Lahiri, Anurag Tiwari	A 140µA 34ppm/°C 30MHz Clock Oscillator in 28nm CMOS Bulk Process.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Abhijit Giri, S. K. Nandy	Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Nitin Gupta, Phalguni Bala, Vijay Kumar Singh	Area & Power Efficient 3.4Gbps/Channel HDMI Transmitter with Single-Ended Structure.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Lou Scheffer	Keynote talk: Deciphering the brain, cousin to the chip.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Kartikeya Bhardwaj, Bharat M. Deshpande	K-Algorithm: An Improved Booth's Recoding for Optimal Fault-Tolerant Reversible Multiplier.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu	Sneak-path Testing of Memristor-based Memories.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Prabhat Avasare, Nitin Chandrachoodan	Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to Silicon.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Ons Mbarek, Alain Pegatoquet, Michel Auguin, Houssem Eddine Fathallah	Power-Aware Wrappers for Transaction-Level Virtual Prototypes: A Black Box Based Approach.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti	Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Somnath Kundu, Shouri Chatterjee	A 44 GHz Quadrature Traveling Wave Oscillator.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee	A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Praveen Venkataramani, Vishwani D. Agrawal	Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Aatmesh Shrivastava, Jagdish Nayayan Pandey, Brian P. Otis, Benton H. Calhoun	A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Supriya Aggarwal, Kavita Khare	Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Debajit Bhattacharya, Ashis Maity, Amit Patra	Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan	Power Supply Efficiency Aware Server Allocation in Data Centers.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	M. Santhosh Prabhu, Pallab Dasgupta	Model Checking Controllers with Predicate Inputs.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	Vijaykrishnan Narayanan	Keynote talk: Embedded vision systems.	VLSI Design	2013	DBLP DOI BibTeX RDF
1	P. Balasubramanian, David A. Edwards, W. B. Toms	Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Khaled Jerbi, Mickaël Raulet, Olivier Déforges, Mohamed Abid	Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Lilia Zaourar, Yann Kieffer, Chouki Aktouf	A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Zhen-dong Zhang, Bin Wu, Yu-mei Zhou, Xin Zhang	Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari	Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Dionysios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris	A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Christina Gimmler-Dumont, Frank Kienle, Bin Wu, Guido Masera	A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Maxwell Walton, Omar Ahmed, Gary William Grewal, Shawki Areibi	An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Maurizio Martina, Muhammad Shafique, Andrey Norkin	VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Muhammad Awais, Carlo Condo	Flexible LDPC Decoder Architectures.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Massimo Bariani, Paolo Lambruschini, Marco Raggio	An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Khaled Grati, Nadia Khouja, Bertrand Le Gal, Adel Ghazel	Power Consumption Models for Decimation FIR Filters in Multistandard Receivers.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Roberta Piscitelli, Andy D. Pimentel	A Signature-Based Power Model for MPSoC on FPGA.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha	Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sergio Saponara, Luca Fanucci	Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick	A New Length-Based Algebraic Multigrid Clustering Algorithm.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	D. S. Harish Ram, M. C. Bhuvaneswari, Shanthi S. Prabhu	A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Guilherme Corrêa, Daniel Palomino, Cláudio Machado Diniz, Sergio Bampi, Luciano Volcan Agostini	Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.	VLSI Design	2012	DBLP DOI BibTeX RDF

Publications at "VLSI Design"( http://dblp.L3S.de/Venues/VLSI_Design )