Search results for "VLSI Design"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Zhen-dong Zhang, Bin Wu, Yu-mei Zhou, Xin Zhang	Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Maxwell Walton, Omar Ahmed, Gary William Grewal, Shawki Areibi	An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Roberta Piscitelli, Andy D. Pimentel	A Signature-Based Power Model for MPSoC on FPGA.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha	Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh	9T Full Adder Design in Subthreshold Region.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer	Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, Todor Stefanov	Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal, Srimat T. Chakradhar (eds.)	25th International Conference on VLSI Design, VLSID 2012, Hyderabad, India, January 7-11, 2012	VLSI Design	2012	DBLP BibTeX RDF
1	Sumit Adhikari, Markus Damm, Christoph Grimm, François Pécheux	Tutorial T1: Design of Mixed-Signal Systems using SystemC AMS Extensions.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez	Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia	SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Samiran Dam, Pradip Mandal	Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Susmita Sur-Kolay, Swarup Bhunia	Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Pinaki Chakrabarti	Clock Tree Skew Minimization with Structured Routing.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Debashis Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee	Power Aware Post-Manufacture Tuning of MIMO Receiver Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Rajesh Gupta	Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Prateek Verma, Preeti Rao	Real-time Melodic Accompaniment System for Indian Music Using TMS320C6713.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese	HD Resolution Intra Prediction Architecture for H.264 Decoder.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Nishit Ashok Kapadia, Sudeep Pasricha	A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Zhe Wang, Sanjay Ranka, Prabhat Mishra	Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Somnath Banerjee, Tushar Gupta	Efficient Online RTL Debugging Methodology for Logic Emulation Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	M. Pramod, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy	CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Amitava Ghosh, Isha Das, Achintya Halder	An Energy Efficient Oscillator Frequency Calibration Methodology Using Fraction Phase Computation.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Ankur Goel, Donald Evans, Richard Stephani, Venkateswara Reddy, Dharmendra Rai, Veerabadra Chary, N. Sathisha	An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Ankit Kagliwal, Shankar Balachandran	Set-Cover Heuristics for Two-Level Logic Minimization.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar	Two Graph Based Circuit Simulator for PDE-Electrical Analogy.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sudeep Pasricha	A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Raguram Damodaran, Timothy Anderson, Sanjive Agarwala, Rama Venkatasubramanian, Michael Gill, Dhileep Gopalakrishnan, Anthony M. Hill, Abhijeet Chachad, Dheera Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, Shriram Moharil, Matthew Pierson, Steven Mullinnix, Hung Ong, David Thompson, Krishna Gurram, Oluleye Olorode, Nuruddin Mahmood, Jose Flores, Arjun Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman	A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Nitin Gupta, Tapas Nandy, Phalguni Bala	Self-Induced Supply Noise Reduction Technique in GBPS Rate Transmitters.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Nilanjan Chattaraj, Anindya Sundar Dhar	Random Access Analog Memory (RA2M) for Video Signal Application.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sajib Kumar Mitra, Ahsan Raja Chowdhury	Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Tarun Kumar Agarwal, M. Jagadesh Kumar	Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	C. J. Janraj, T. Venkata Kalyan, Tripti Warrier, Madhu Mutyam	Way Sharing Set Associative Cache Architecture.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	Keynote Talk: A History of the VLSI Design Conference.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Lei Wang, Somnath Paul, Swarup Bhunia	Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Arvind Jain, Maheedhar Jalasutram, Srinivas Vooka, Prasun Nair, Neeraj Pradhan	At-speed Testing of Asynchronous Reset De-assertion Faults.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, Nagarajan Ranganathan	Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Supriyo Maji, Pradip Mandal	A Fast Equation Free Iterative Approach to Analog Circuit Sizing.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Anindya Lal Roy, Anirban Bhattacharya, Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya	Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Ankit More, Baris Taskin	3-D Parasitic Modeling for Rotary Interconnects.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Angada B. Sachid, P. Paliwal, S. Joshi, M. Shojaei, D. Sharma, V. Ramgopal Rao	Circuit Optimization at 22nm Technology Node.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar	A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur	A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Bodhisatwa Mazumdar, Debdeep Mukhopadhyay, Indranil Sengupta	Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Subhajit Sen, Dan Babitch, Noshir Dubash	A Compact Temperature Sensor at 1.8µA per Hz Conversion Rate and 1.1 °C Accuracy for SOCs.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Hadi Hajimiri, Prabhat Mishra	Intra-Task Dynamic Cache Reconfiguration.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Jinpeng Lv, Priyank Kalla	Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Kameswara Rao B., Muralidhar Reddy B., Ravi Kishore B.	Tutorial T8B: Wireless System Design and Systems Engineering Challenges.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Saravana Kumar, Shouri Chatterjee	A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Jean-Michel Chabloz, Ahmed Hemani	Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy	Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Ritwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, Parthasarathi Dasgupta	A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Deepa N. Sarma, Gopalakrishnan Lakshminarayanan, K. V. R. Suryakiran Chavali	A Novel Encoding Scheme for Low Power in Network on Chip Links.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Cory E. Merkel, Dhireesha Kudithipudi	Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Debjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay	A Library for Passive Online Verification of Analog and Mixed-Signal Circuits.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sathyam K. Pattanam, P. P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, Vikas Gautham, Raju Bala Showry Pudota	Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Annajirao Garimella, Punith R. Surkanti, Paul M. Furth	Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha	Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Warin Sootkaneung, Kewal K. Saluja	Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Pawan Kumar Moyade, Nandakumar Nambath, Allmin Ansari, Shalabh Gupta	Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Priyadharshini Shanmugasundaram, Vishwani D. Agrawal	Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Mahima Arrawatia, Varish Diddi, Harsha Kochar, Maryam Shojaei Baghini, Girish Kumar	An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Unmesh D. Bordoloi, Bharath Suri, Swaroop Nunna, Samarjit Chakraborty, Petru Eles, Zebo Peng	Customizing Instruction Set Extensible Reconfigurable Processors Using GPUs.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Joshua W. Wells, Jayaram Natarajan, Abhijit Chatterjee, Irtaza Barlas	Real-Time, Content Aware Camera - Algorithm - Hardware Co-Adaptation for Minimal Power Video Encoding.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Shankar Hemmady	Tutorial T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	S. K. Sahoo, K. Srinivasa Reddy	A High Speed FIR Filter Architecture Based on Novel Higher Radix Algorithm.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Srikanth Venkataraman, Nagesh Tamarapalli	Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	M. Kalyana Kumar Rao, Shantha Kumari P. V., Boopalan Sellappan	Embedded Tutorial ET2: Digital Subscriber Line.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Manas Kumar Hati, Tarun Kanti Bhattacharyya	A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Kamalika Datta, Gaurav Rathi, Indranil Sengupta, Hafizur Rahaman	Synthesis of Reversible Circuits Using Heuristic Search Method.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Siva Kothamasu	Embedded Tutorial ET3: Packaging Trends, Die Package Co-Design Flow and Challenges.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Bert Gyselinckx	Keynote Talk: A Wireless Sensor a Day Keeps the Doctor Away.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Dhiraj Reddy Nallapa Yoge, Nitin Chandrachoodan	GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Nikil Dutt, Mani B. Srivastava, Rajesh Gupta, Subhashish Mitra	Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Mohit Singh, Shalabh Gupta	Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DAC.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Samarjit Chakraborty	Keynote Talk: Challenges in Automotive Cyber-physical Systems Design.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Vijay Raghunathan	Embedded Tutorial ET4: Advanced Techniques for Programming Networked Embedded Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sujan K. Manohar, Ramakrishnan Venkatasubramanian, Poras T. Balsara	Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Rajesh A. Patil, Gauri Gupta, Vineet Sahula, A. S. Mandal	Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker	Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Jaswinder S. Ahuja	Keynote Talk: Semiconductor Industry: Best of Times, Worst of Times, and Nowhere Else I Would Rather Be!	VLSI Design	2012	DBLP DOI BibTeX RDF
1	David Atienza, Arvind Sridhar	Tutorial T7A: New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the Future.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sujan K. Manohar, Vinod K. Somasundar, Ramakrishnan Venkatasubramanian, Poras T. Balsara	Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Supriya Aggarwal, Kavita Khare	Hardware Efficient Architecture for Generating Sine/Cosine Waves.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu	Eliminating Performance Penalty of Scan.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Breeta SenGupta, Urban Ingelsson, Erik Larsson	Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram	A Novel SMT-Based Technique for LFSR Reseeding.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	H. C. Srinivasaiah	Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Anandaroop Ghosh, Somnath Paul, Swarup Bhunia	Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Deepak Kumar Meher, Arunkumar Salimath, Achintya Halder	An Ultra-low Power Symbol Detection Methodology and Its Circuit Implementation for a Wake-up Receiver in Wireless Sensor Nodes.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Srinivas Vooka, Khushboo Agarwal, Abhijeet Shrivastava, Pranav Murthy, Ramakrishnan Venkatraman	A Silicon Testing Strategy for Pulse-Width Failures.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Ajay Joshi	Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Junyoung Park, H. Mert Ustun, Jacob A. Abraham	Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Liang Tang, Jorgen Peddersen, Sri Parameswaran	A Rapid Methodology for Multi-mode Communication Circuit Generation.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Annajirao Garimella, Punith R. Surkanti, Paul M. Furth	Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee	Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method.	VLSI Design	2011	DBLP DOI BibTeX RDF

Publications at "VLSI Design"( http://dblp.L3S.de/Venues/VLSI_Design )