Search results for "VLSI Design"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee	Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Haipeng Zhang, Ruisheng Qi, Liang Zhang, Buchun Su, Dejun Wang	Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Debasri Saha, Susmita Sur-Kolay	SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson, Jiang Hu	Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Soumya Pandit, Chittaranjan A. Mandal, Amit Patra	A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	I. Hameem Shanavas, Ramaswamy Kannan Gnanamurthy	Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan	Shedding Physical Synthesis Area Bloat.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Dongjin Lee, Igor L. Markov	CONTANGO: Integrated Optimization of SoC Clock Networks.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Guanyi Sun, Shengnan Xu, Xu Wang, Dawei Wang, Eugene Tang, Yangdong Deng, Sun Chan	A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Subhra Dhar, Manisha Pattanaik, Poolla Rajaram	Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Tareq Hasan Khan, Khan A. Wahid	Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee	Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Yoni Aizik, Avinoam Kolodny	Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto	Buffer Planning for IP Placement Using Sliced-LFF.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	T. Suresh, K. L. Shunmuganathan	Efficient Resource Sharing Architecture for Multistandard Communication System.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	The Impact of Statistical Leakage Models on Design Yield Estimation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Jacqueline E. Rice, Jon C. Muzio, Neil Anderson	New Considerations for Spectral Classification of Boolean Switching Functions.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Mrigank Sharad, P. Vijaya Sankara Rao, Pradip Mandal	A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Praveen K. Meduri, Shirshak K. Dhali	A Methodology for Automatic Transistor-Level Sizing of CMOS OpAmps.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Vignesh Vivekraja, Leyla Nazhandali	Feedback Based Supply Voltage Control for Temperature Variation Tolerant PUFs.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas	A Robust and Reconfigurable Multi-mode Power Gating Architecture.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Hussam Amrouch, Joerg Henkel	Self-Immunity Technique to Improve Register File Integrity Against Soft Errors.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Aritra Banerjee, Vishwanath Natarajan, Shreyas Sen, Abhijit Chatterjee, Ganesh Srinivasan, Soumendu Bhattacharya	Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Parag Kulkarni, Puneet Gupta, Milos Ercegovac	Trading Accuracy for Power with an Underdesigned Multiplier Architecture.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Vivek T. D, Olivier Sentieys, Steven Derrien	Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Subhankar Mukherjee, Pallab Dasgupta	Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Michael B. Henry, Robert Lyerly, Leyla Nazhandali, Adam Fruehling, Dimitrios Peroulis	MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Aarul Jain, Aviral Shrivastava, Chaitali Chakrabarti	LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Maheshwar Chandrasekar, Michael S. Hsiao	A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	M. Zhang, R. Haussler, Markus Olbrich, Harald Kinzelbach, Erich Barke	A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	K. C. Narasimhamurthy, Roy P. Paily	Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Sandesh Prabhakar, Rajamani Sethuram, Michael S. Hsiao	Trace Buffer-Based Silicon Debug with Lossless Compression.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Michael Trakimas, Sungkil Hwang, Sameer R. Sonkusale	Low Power Asynchronous Data Acquisition Front End for Wireless Body Sensor Area Network.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Srabanti Pandit, Chandan Kumar Sarkar	Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Sreekanth Soman, Amit Brahme, Ramakrishnan Venkatraman, Raashid Shaikh, Santhosh Thiyagaraja, Mahendrasing Patil	Ensuring On-Die Power Supply Robustness in High-Performance Designs.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Sudip Roy, Bhargab B. Bhattacharya, Partha Pratim Chakrabarti, Krishnendu Chakrabarty	Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak	A 1.8GHz Digital PLL in 65nm CMOS.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan	Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Pei Liu, Ahmed Hemani, Kolin Paul	A Reconfigurable Processor for Phylogenetic Inference.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Sambit Datta, Ashudeb Dutta, Kunal Datta, Tarun Kanti Bhattacharyya	Pseudo Concurrent Quad-Band LNA Operating in 900 MHz/1.8 GHz and 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Palkesh Jain, Ankit Jain	Accurate Estimation of Signal Currents for Reliability Analysis Considering Advanced Waveform-Shape Effects.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Reeshav Kumar, Yoon Seok Yang, Gwan Choi	Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Su Myat Min, Jorgen Peddersen, Sri Parameswaran	Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski	Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.	VLSI Design	2011	DBLP DOI BibTeX RDF
1		VLSI Design 2011: 24th International Conference on VLSI Design, IIT Madras, Chennai, India, 2-7 January 2011	VLSI Design	2011	DBLP BibTeX RDF
1	Ashis Maity, Amit Patra, Norihisa Yamamura, Jonathan Knight	Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Srinivasaraman Chandrasekaran, Kunal Desai, Arul Sendhil, William Ng	Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kiran Kumar Abburi	A Scalable LDPC Decoder on GPU.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty	4×2Gbps Source-Synchronous Transmitter in 45nm CMOS.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose	An Approach to Tolerate Process Related Variations in Memristor-Based Applications.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Vikram Chaturvedi, Bharadwaj Amrutur	A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kautalya Mishra, Ahmed Faraz, Adit D. Singh	Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan	Thermal-Aware Test Scheduling Using On-chip Temperature Sensors.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Ayan Mandal, Nikhil Jayakumar, Kalyana C. Bollapalli, Sunil P. Khatri, Rabi N. Mahapatra	An Automated Approach for Minimum Jitter Buffered H-Tree Construction.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Subha Chakraborty, T. K. Bhattacharyya	Development of a Micro-mechanical Logic Inverter for Low Frequency MEMS Sensor Interfacing.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kunal Desai, Vijay Krishna	Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat	Power Scalable Digital Baseband Architecture for IEEE 802.15.4.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur	Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Diptendu Ghosh, Ranjit Gharpurey	Evolution of Oscillation in a Quadrature Oscillator.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Yi-Ling Hsieh, Tsung-Yi Ho	Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani, Sridharan Moorthi	NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Bhaskar Gopalan	A SPICE Macromodel for the Analysis of Lossy Dispersive Coupled GaAs Interconnect Line System.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	J. Manikandan, B. Venkataramani, K. Girish, H. Karthic, V. Siddharth	Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kashfia Haque, Paul Beckett	A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi	Multi-CoDec Configurations for Low Power and High Quality Scan Test.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Maheshwar Chandrasekar, Michael S. Hsiao	Fault Collapsing Using a Novel Extensibility Relation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kartik Shrivastava, Prabhat Mishra	Dual Code Compression for Embedded Systems.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Sachin Shrivastava, Harindranath Parameswaran	Improved Timing Windows Overlap Check Using Statistical Timing Analysis.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Omer Malik, Ahmed Hemani, Muhammad Ali Shami	A Library Development Framework for a Coarse Grain Reconfigurable Architecture.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa	Extraction of Aspect Ratio for Non-Manhattan CMOS Devices.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Dinesh Ganta, Vignesh Vivekraja, Kanu Priya, Leyla Nazhandali	A Highly Stable Leakage-Based Silicon Physical Unclonable Functions.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Sipra Mandal, Soumya Pandit	Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Jayanand Asok Kumar, Shobha Vasudevan	Variation-Conscious Formal Timing Verification in RTL.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Swapnil Lotlikar, Vinayak Pai, Paul V. Gratz	AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Ayan Mandal, Vinay Karkala, Sunil P. Khatri, Rabi N. Mahapatra	Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Anupam Dutta, T. K. Bhattacharyya	Low Offset, Low Noise, Variable Gain Interfacing Circuit with a Novel Scheme for Sensor Sensitivity and Offset Compensation for MEMS Based, Wheatstone Bridge Type, Resistive Smart Sensor.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Weixun Wang, Sanjay Ranka, Prabhat Mishra	A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kanad Basu, Prabhat Mishra	Efficient Trace Signal Selection for Post Silicon Validation and Debug.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	V. R. Devanathan, Ishaan Santhosh Shah	Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Tapas Kumar Kundu, Kolin Paul	Improving Android Performance and Energy Efficiency.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala	A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Kyungseok Kim, Vishwani D. Agrawal	True Minimum Energy Design Using Dual Below-Threshold Supply Voltages.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Keerthi Kunaparaju, Seetharam Narasimhan, Swarup Bhunia	VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Reza Hashemian	Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Jun Zhao, Yong-Bin Kim	A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Gregory D. Peterson, Ethan Farquhar, Benjamin J. Blalock	Selected Papers from the Midwest Symposium on Circuits and Systems.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Boppana Lakshmi, A. S. Dhar	CORDIC Architectures: A Survey.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Akila Gothandaraman, Gregory D. Peterson, G. Lee Warren, Robert J. Hinde, Robert J. Harrison	A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Chandradevi Ulaganathan, Neena Nambiar, Kimberly Cornett, Robert L. Greenwell, Jeremy A. Yager, Benjamin S. Prothro, Kevin Tham, Suheng Chen, Richard S. Broughton, Guoyuan Fu, Benjamin J. Blalock, Charles L. Britton Jr., M. Nance Ericson, H. Alan Mantooth, Mohammad M. Mojarradi, Richard W. Berger, John D. Cressler	A SiGe BiCMOS Instrumentation Channel for Extreme Environment Applications.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	P. Sumathi, P. A. Janakiraman	FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Bo Marr, Jason George, Brian P. Degnan, David V. Anderson, Paul E. Hasler	Error Immune Logic for Low-Power Probabilistic Computing.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	JunKyu Lee, Gregory D. Peterson, Robert J. Harrison, Robert J. Hinde	Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Yao Xu, Ashok Kumar Srivastava, Ashwani K. Sharma	Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Post-CTS Delay Insertion.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Kamakshy Selvajyothi, P. A. Janakiraman	FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Tooraj Nikoubin, Poona Bahrebar, Sara Pouri, Keivan Navi, Vaez Iravani	Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Saumil Merchant, Gregory D. Peterson	Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Sergio Saponara, Tommaso Baldetti, Luca Fanucci	A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation.	VLSI Design	2010	DBLP DOI BibTeX RDF

Publications at "VLSI Design"( http://dblp.L3S.de/Venues/VLSI_Design )