Search results for "VLSI circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin	A memory aware behavioral synthesis tool for real-time VLSI circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	memory aware, behavioral synthesis, VLSI circuits
3	Witold A. Pleskacz	Yield Estimation of VLSI Circuits with Downscaled Layouts. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	IC layout scaling, VLSI circuits, critical area, spot defects, manufacturing yield
3	K. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto, Y. Umehara, J. Matsumoto	Novel Optical Probing System for Quarter-micron VLSI Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Internal analysis, Prober, Electro-optic Sampling, Scanning Force Microscope, waveform, DC voltage, VLSI Circuits
3	S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	programmable cellular automata, polynomial algebraic tools, faulty signatures, multiple attractor, fault dictionary size, cascadable structure, VLSI, fault diagnosis, fault diagnosis, logic testing, partitions, cellular automata, integrated circuit testing, automatic testing, VLSI circuits, logic partitioning, signature analyzer
3	Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth	Analog VLSI circuits for manufacturing inspection.	ARVLSI	1995	DBLP DOI BibTeX RDF	analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits
3	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
2	Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang	A novel ACO-based pattern generation for peak power estimation in VLSI circuits.	ISQED	2009	DBLP DOI BibTeX RDF
2	Chong Zhao, Yi Zhao, Sujit Dey	Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	J. V. R. Ravindra, M. B. Srinivas	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	krylov subspace techniques, monte-carlo simulation, model order reduction, rlc
2	Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack	NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	modeling, crosstalk, static timing analysis
2	Yu Zhong, Martin D. F. Wong	Fast Placement Optimization of Power Supply Pads.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.398 to 0.196 V, power supply pads, power grid networks, voltage deviation, 72 mins, 0.134 to 0.024 V, simulated annealing, iterative method, VLSI circuits
2	Zhao Li, C.-J. Richard Shi	SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Chong Zhao, Sujit Dey	Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO).	ISQED	2006	DBLP DOI BibTeX RDF
2	Hemant Mahawar, Vivek Sarin	Parallel algorithms for inductance extraction of VLSI circuits.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Adam Slowik, Michal Bialko	Partitioning of VLSI Circuits on Subcircuits with Minimal Number of Connections Using Evolutionary Algorithm.	ICAISC	2006	DBLP DOI BibTeX RDF
2	Mohammed Bougataya, Ahmed Lakhsasi, Daniel Massicotte	Steady State Thermo-mechanical Stress Prediction for Large VLSI circuits using GDS Method.	CCECE	2006	DBLP DOI BibTeX RDF
2	Amardeep Singh, Lalit M. Bharadwaj, Singh Harpreet	DNA and quantum based algorithms for VLSI circuits testing.	Natural Computing	2005	DBLP DOI BibTeX RDF	DNA algorithm, genetic algorithms, neural networks, ATPG, quantum computation, quantum algorithm
2	Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri	Fault diagnosis of VLSI circuits with cellular automata based pattern classifier.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	W. W. Bachmann, Sorin A. Huss	Efficient algorithms for multilevel power estimation of VLSI circuits.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Shiyi Xu	High-Order Syndrome Testing for VLSI Circuits.	PRDC	2005	DBLP DOI BibTeX RDF	Syndrome Testing Minterms, Syndrome, Exhaustive Testing
2	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
2	James B. Kuo	Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
2	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Koichiro Noguchi, Makoto Nagata	On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits.	DATE	2005	DBLP DOI BibTeX RDF
2	Bartomeu Alorda, Sebastiàn A. Bota, Jaume Segura	A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF	Current based testing, built-in current monitors, high-speed measurements, transient current
2	Christopher J. Augeri, Hesham H. Ali	New graph-based algorithms for partitioning VLSI circuits.	ISCAS	2004	DBLP DOI BibTeX RDF
2	Hasan Arslan, Shantanu Dutt	A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits.	ICCD	2004	DBLP DOI BibTeX RDF
2	Atul Maheshwari, Israel Koren, Wayne Burleson	Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits.	DFT	2003	DBLP DOI BibTeX RDF
2	Shantanu Dutt, Wenyong Deng	Cluster-aware iterative improvement techniques for partitioning large VLSI circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	VLSI circuit partitioning, mincut, physical design/layout, Clusters, iterative-improvement
2	Patrick Girard	Survey of Low-Power Testing of VLSI Circuits.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini, Haydar Hadi	A Novel Analytical Model for Evaluation of Substrate Crosstalk in VLSI Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Substrate coupling modeling, image method, Green's function
2	Hemant Mahawar, Vivek Sarin, Weiping Shi	Fast Inductance Extraction of Large VLSI Circuits. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	Inductance extraction, VLSI, parallel computing, iterative methods, preconditioning
2	Cristian Constantinescu	Impact of Deep Submicron Technology on Dependability of VLSI Circuits.	DSN	2002	DBLP DOI BibTeX RDF
2	Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev	Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Qing Wu, Qinru Qiu, Massoud Pedram	Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	Mukul R. Prasad, Philip Chong, Kurt Keutzer	Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	combinational ATPG, SAT, backtracking, complexity analysis, VLSI circuits
2	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.	FPL	2001	DBLP DOI BibTeX RDF
2	Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu	Interconnect implications of growth-based structural models for VLSI circuits.	SLIP	2001	DBLP DOI BibTeX RDF
2	Dilip K. Bhavsar, Rishan Tan	Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly	Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig	Self-reorganising systems on VLSI circuits.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	FPGA, dependability, Fault detection, Fault Injection
2	Bassam Shaer, David L. Landis, Sami A. Al-Arian	Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj	Power Bus Maximum Voltage Drop in Digital VLSI Circuits.	ISQED	2000	DBLP DOI BibTeX RDF
2	Norbert Fröhlich, Volker Gloeckel, Josef Fleischmann	A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level.	DATE	2000	DBLP DOI BibTeX RDF
2	J. A. Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca	A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Sensor, CMOS, Crosstalk, Digital
2	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
2	Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly	A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Li-Rong Zheng, Hannu Tenhunen	Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	Mixed-Signal VLSI, Interconnection, Crosstalk, Noise Margin
2	Tomasz Garbolino, Andrzej Hlawiczka	A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits.	EDCC	1999	DBLP DOI BibTeX RDF
2	Li-Rong Zheng, Hannu Tenhunen	Effective power and ground distribution scheme for deep submicron high speed VLSI circuits.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Kevin T. Tang, Eby G. Friedman	Peak noise prediction in loosely coupled interconnect [VLSI circuits].	ISCAS	1999	DBLP DOI BibTeX RDF
2	Amar Guettaf, Pirouz Bazargan-Sabet	Efficient Partitioning Method For Distributed Logic Simulation of VLSI Circuits.	Annual Simulation Symposium	1998	DBLP DOI BibTeX RDF
2	Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu	A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.	ITC	1998	DBLP DOI BibTeX RDF
2	Michael Orshansky, James C. Chen, Chenming Hu	A Statistical Performance Simulation Methodology for VLSI Circuits.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
2	M.-N. Sabry, A. Bontemps, V. Aubert, R. Vahrmann	Realistic and efficient simulation of electro-thermal effects in VLSI circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Abby A. Ilumoka	Modular artificial neural network models for simulation and optimization of VLSI circuits.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	modular artificial neural network models, MANN, process level parameters, optimization, circuit analysis computing, VLSI circuits, modular neural network, circuit performance
2	Norbert Fröhlich, Rolf Schlagenhaft, Josef Fleischmann	A New Approach for Partitioning VLSI Circuits on Transistor Level.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF
2	Tzuhao Chen, Ibrahim N. Hajj	GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment.	ICCAD	1997	DBLP DOI BibTeX RDF	GOLDENGATE, digital VLSI circuits, electrical-level simulation, event-driven technique, logic/I/sub DDQ/ testing, logic testing, sequential circuits, combinational circuits, bridging fault simulator
2	Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel	Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF	asynchronous parallel algorithms, dynamic characteristics, redundant work, sequential VLSI circuits, synchronous two stage approach, test set partitioned fault simulation, MPI, Message Passing Interface, shared memory multiprocessor, circuit analysis computing, circuit CAD, software portability
2	Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	simulation-based test generation, distributed memory MIMD machines, shared memory MIMD machines, parallel search strategies, logic testing, fault coverage, NP-complete problems, VLSI circuits, parallel genetic algorithms, sequential circuit test generation
2	Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation.	VTS	1997	DBLP DOI BibTeX RDF	SPITFIRE, scalable parallel algorithms, test set partitioned fault simulation, synchronous parallel algorithms, sequential VLSI circuits, VLSI, fault coverage
2	Y. G. Chen, James B. Kuo	A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
2	Daniel G. Saab, Youssef Saab, Jacob A. Abraham	Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
2	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
2	Prathima Agrawal, B. Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
2	S. Sundaram, Lalit M. Patnaik	Distributed logic simulation: time-first evaluation vs. event driven algorithms.	VLSI Design	1996	DBLP DOI BibTeX RDF	distributed logic simulation, time-first evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation
2	Chuan-Yu Wang, Kaushik Roy	Maximum power estimation for CMOS circuits using deterministic and statistic approaches.	VLSI Design	1996	DBLP DOI BibTeX RDF	maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach
2	Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj	Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Wen-Ben Jone, Christos A. Papachristou	A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
2	Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak	An improved output compaction technique for built-in self-test in VLSI circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
2	Hirendu Vaishnav, Massoud Pedram	Delay optimal partitioning targeting low power VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	clustering, VLSI, partitioning, logic CAD, circuit CAD, integrated logic circuits, power dissipation, VLSI circuits, logic partitioning, delay optimal
2	Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang	Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	maximum switching activity, uncertainty waveforms, circuit reliability
2	K. K. Lai, P. H. W. Leong	An area efficient implementation of a cellular neural network.	ANNES	1995	DBLP DOI BibTeX RDF	area efficient implementation, time multiplexing scheme, higher density implementations, neural circuits, simulation, VLSI, edge detection, edge detection, circuit analysis computing, VLSI circuits, cellular neural network, neural chips, cellular logic, cellular neural nets
2	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
2	Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barros, Raúl Jiménez, José L. Huertas	New CMOS VLSI linear self-timed architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
2	Yinghua Min, Zhuxing Zhao, Zhongcheng Li	Boolean process-an analytical approach to circuit representation (II).	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	waveform analysis, circuit representation, logical behavior, waveform functions, mathematical tools, waveform polynomials, input transitions, VLSI, Boolean functions, timing, design for testability, logic design, logical design, polynomials, integrated circuit design, VLSI circuits, performance enhancement, timing behavior, Boolean process, circuit delay
2	Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis	An efficient comparative concurrent Built-In Self-Test technique.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
2	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
2	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
2	S. C. Prasad, Kaushik Roy	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
2	Sudhir M. Gowda, Bing J. Sheu	BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Farid N. Najm	A survey of power estimation techniques in VLSI circuits.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
2	G. Masseboeuf, J. Pulou, J. L. Rainard	Hierarchical Test Analysis of VLSI Circuits for Random BIST.	EDCC	1994	DBLP DOI BibTeX RDF
2	Wolfgang T. Eisenmann, Helmut E. Graeb	Fast transient power and noise estimation for VLSI circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
2	Dorothy E. Setliff, Rob A. Rutenbar	Knowledge Representation and Reasoning in a Software Synthesis Architecture.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	software synthesis architecture, reasoning strategies, automatic program synthesis architecture, ELF, procedure-level decomposition, synthetic router, data structures, knowledge representation, knowledge representation, computer-aided design, inference mechanisms, automatic programming, circuit layout CAD, design space, VLSI circuits, domain-specific knowledge
2	Meryem Marzouki	Model-based reasoning for electron-beam debugging of VLSI circuits.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	Electron-beam testing, second generation KBS, VLSI circuit diagnosis, model-based reasoning
2	Matthias Passlack, Manfred Uhle, Horst Elschner	Analysis of propagation delays in high-speed VLSI circuits using a distributed line model.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
2	Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj	Probabilistic simulation for reliability analysis of CMOS VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
2	Andrzej Krasniewski, Slawomir Pilarski	Circular self-test path: a low-cost BIST technique for VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
2	Çetin Kaya Koç, P. F. Ordung	Schwarz-Christoffel transformation for the simulation of two-dimensional capacitance [VLSI circuits].	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
2	Wen-Ben Jone, Christos A. Papachristou, M. Pereira	A Scheme for Overlaying Concurrent Testing of VLSI Circuits.	DAC	1989	DBLP DOI BibTeX RDF
2	Sudipta Bhawmik, P. Pal Chaudhuri	DFTEXPERT: An Expert System for Design of Testable VLSI Circuits.	IEA/AIE (Vol. 1)	1988	DBLP DOI BibTeX RDF
2	Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder	A Notation for Describing Multiple Views of VLSI Circuits.	DAC	1988	DBLP BibTeX RDF
1	S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha	Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Makoto Nagata, Vivek De	Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Luca Henzen	VLSI circuits for cryptographic authentication.		2011	RDF
1	Wagah Farman Mohammad	New Analysis to Measure the Capacitance and Conductance of MOS Structure toward Small Size of VLSI Circuits.	Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Eero Ivask, Sergei Devadze, Raimund Ubar	Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits.	Scalable Computing: Practice and Experience	2011	DBLP BibTeX RDF