Search results for "VLSI design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Si-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar	Routing using implicit connection graphs [VLSI design.	VLSI Design	1996	DBLP DOI BibTeX RDF	implicit connection graphs, shortest path related problems, minimum spanning tree problem, sparse strong connection graph, large VLSI design applications, VLSI, graph theory, search problems, circuit layout CAD, VLSI layout, integrated circuit layout, obstacles, search behavior
4	Jens Lienig	Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach.	VLSI Design	1997	DBLP DOI BibTeX RDF	minimized crosstalk, interconnection routing, interconnection crosstalk, VLSI channel routing, VLSI switchbox routing, distributed workstation network, VLSI, VLSI design, parallel genetic algorithm
4	Luca Penzo, Donatella Sciuto, Cristina Silvano	VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes.	VLSI Design	1995	DBLP DOI BibTeX RDF	odd-weight-column byte error detection, SEC-DED codes, single error correction, double error detection, single byte error detection, SEC-DED-SBD codes, high performances VLSI implementations, high speed encoding/decoding circuits, parallel data manipulation, VHSIC Hardware Description Language, VHDL description, parallel processing, VLSI, software tool, error correction codes, application specific integrated circuits, logic CAD, decoding, VLSI design, error detection codes, hardware description languages, integrated logic circuits, digital integrated circuits
3	Vishwani D. Agrawal	Keynote Talk: A History of the VLSI Design Conference.	VLSI Design	2012	DBLP DOI BibTeX RDF
3	Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam	Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.	VLSI Design	2009	DBLP DOI BibTeX RDF
3	Debasri Saha, Susmita Sur-Kolay	Encoding of Floorplans through Deterministic Perturbation.	VLSI Design	2009	DBLP DOI BibTeX RDF
3	Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.	VLSI Design	2009	DBLP DOI BibTeX RDF
3	Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta	A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment.	VLSI Design	2009	DBLP DOI BibTeX RDF
3	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind	An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
3	Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif	Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.	VLSI Design	2008	DBLP DOI BibTeX RDF
3	Charbel J. Akl, Magdy A. Bayoumi	Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling.	VLSI Design	2008	DBLP DOI BibTeX RDF
3	Jiajin Tu, Jian Chen, Lizy K. John	Hardware Efficient Piecewise Linear Branch Predictor.	VLSI Design	2007	DBLP DOI BibTeX RDF
3		VLSI Design 2005 Conference Awards.	VLSI Design	2006	DBLP DOI BibTeX RDF
3		VLSI Design Conference History.	VLSI Design	2006	DBLP DOI BibTeX RDF
3		Call for Participation: 10th IEEE VLSI Design & Test Symposium.	VLSI Design	2006	DBLP DOI BibTeX RDF
3		VLSI Design 2006 Conference Awards.	VLSI Design	2006	DBLP DOI BibTeX RDF
3		Call for Participation: VLSI Design 2007.	VLSI Design	2006	DBLP DOI BibTeX RDF
3	Shekhar Y. Borkar	VLSI Design Challenges for Gigascale Integration. (PDF / PS)	VLSI Design	2005	DBLP DOI BibTeX RDF
3	Yibo Wang, Yici Cai, Xianlong Hong	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.	VLSI Design	2005	DBLP DOI BibTeX RDF	accurate delay model, obstacle-aware routing, buffer insertion, interconnect optimization
3	Marong Phadoongsidhi, Kewal K. Saluja	Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
3	Masahiro Fujita	Formal Verification of C Language Based VLSI Designs.	VLSI Design	2004	DBLP DOI BibTeX RDF
3	C. P. Ravikumar	Multiprocessor Architectures for Embedded System-on-chip Applications.	VLSI Design	2004	DBLP DOI BibTeX RDF
3	Pranav Anbalagan, Jeffrey A. Davis	Maximum Multiplicity Distributions for Length Prediction Driven Placement.	VLSI Design	2004	DBLP DOI BibTeX RDF
3	A. Vasudevan	Advances in VLSI Design and Product Development Challenges.	VLSI Design	2003	DBLP DOI BibTeX RDF
3	Rajiv V. Joshi, Kaushik Roy	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
3	Biswadip Mitra	Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. (PDF / PS)	VLSI Design	2002	DBLP DOI BibTeX RDF
3	Chunhong Chen	Probabilistic Analysis of Rectilinear Steiner Trees.	VLSI Design	2002	DBLP DOI BibTeX RDF
3	Kuo-Hsing Cheng, Shun-Wen Cheng	Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.	VLSI Design	2002	DBLP DOI BibTeX RDF	full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant
3	Vineet Sahula, C. P. Ravikumar	The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.	VLSI Design	2001	DBLP DOI BibTeX RDF
3	Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar	Theory and Applications of Cellular Automata for VLSI Design and Testing.	VLSI Design	2000	DBLP BibTeX RDF
3	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR
3	Kolin Paul, Dipanwita Roy Chowdhury	Application of GF(2p) CA in Burst Error Correcting Codes.	VLSI Design	2000	DBLP DOI BibTeX RDF
3	Basant Rajan, R. K. Shyamasundar	Modeling VHDL in Multiclock ESTEREL.	VLSI Design	2000	DBLP DOI BibTeX RDF
3	Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra	Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications.	VLSI Design	2000	DBLP DOI BibTeX RDF	ATSC standard, picture processing, VLSI design, video processing, Digital television, HDTV, media processor
3	Juha Plosila, Tiberiu Seceleanu	Design of Synchronous Action Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF
3	P. Ghosh, R. Mangaser, C. Mark, K. Rose	Interconnect-Dominated VLSI Design.	ARVLSI	1999	DBLP DOI BibTeX RDF	Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion
3	Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag	Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.	VLSI Design	1999	DBLP DOI BibTeX RDF
3	Debashis Saha, Anantha Chandrakasan	Web-based Distributed VLSI Design.	VLSI Design	1998	DBLP DOI BibTeX RDF
3	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
3	Gary William Grewal, Thomas Charles Wilson	An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.	VLSI Design	1997	DBLP DOI BibTeX RDF
3	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal	An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.	VLSI Design	1997	DBLP DOI BibTeX RDF	three-layer restricted dogleg routing model, nontrivial lower bound, channel routing problem, two-layer Manhattan routing model, three-layer no-dogleg HVH routing model, two-layer restricted dogleg routing model, vertical constraint graph, VLSI, polynomial time algorithm, VLSI design
3	Prathima Agrawal, B. Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
3	John A. Chandy, Prithviraj Banerjee	Parallel simulated annealing strategies for VLSI cell placement.	VLSI Design	1996	DBLP DOI BibTeX RDF	parallel simulated annealing strategies, VLSI cell placement, cell placement annealing, multiple Markov chains, parallel moves approach, parallel algorithms, VLSI, simulated annealing, Markov processes, VLSI design, circuit layout CAD, integrated circuit layout, speculative computation, standard cell placement
3	Jin-Tai Yan	A simple yet effective genetic approach for the orientation assignment on cell-based layout.	VLSI Design	1996	DBLP DOI BibTeX RDF	genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
3	Natesan Venkateswaran, Dinesh Bhatia	Clock-Skew Constrained Cell Placement.	VLSI Design	1996	DBLP DOI BibTeX RDF
3	Robert Pearson	Linking fabrication and parametric testing to VLSI design courses.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design courses, simulation model parameters, VLSI, integrated circuit testing, integrated circuit design, integrated circuit modelling, educational courses, device models, parametric testing, electronic engineering education
3	B. Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis	The VLSI design and implementation of the array processors of a multilayer vision system architecture.	ASAP	1995	DBLP DOI BibTeX RDF	multilayer vision system architecture, KYDON vision system, multilayered image understanding system, computer vision, parallel processing, VLSI, digital simulation, VLSI design, array processors, timing simulation
3	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
2	Vishwani D. Agrawal, Srimat T. Chakradhar (eds.)	25th International Conference on VLSI Design, VLSID 2012, Hyderabad, India, January 7-11, 2012	VLSI Design	2012	DBLP BibTeX RDF
2	Sumit Adhikari, Markus Damm, Christoph Grimm, François Pécheux	Tutorial T1: Design of Mixed-Signal Systems using SystemC AMS Extensions.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez	Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia	SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Samiran Dam, Pradip Mandal	Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Susmita Sur-Kolay, Swarup Bhunia	Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Pinaki Chakrabarti	Clock Tree Skew Minimization with Structured Routing.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Debashis Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee	Power Aware Post-Manufacture Tuning of MIMO Receiver Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Rajesh Gupta	Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Prateek Verma, Preeti Rao	Real-time Melodic Accompaniment System for Indian Music Using TMS320C6713.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese	HD Resolution Intra Prediction Architecture for H.264 Decoder.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Nishit Ashok Kapadia, Sudeep Pasricha	A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Zhe Wang, Sanjay Ranka, Prabhat Mishra	Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Somnath Banerjee, Tushar Gupta	Efficient Online RTL Debugging Methodology for Logic Emulation Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	M. Pramod, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy	CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Amitava Ghosh, Isha Das, Achintya Halder	An Energy Efficient Oscillator Frequency Calibration Methodology Using Fraction Phase Computation.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Ankur Goel, Donald Evans, Richard Stephani, Venkateswara Reddy, Dharmendra Rai, Veerabadra Chary, N. Sathisha	An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Ankit Kagliwal, Shankar Balachandran	Set-Cover Heuristics for Two-Level Logic Minimization.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar	Two Graph Based Circuit Simulator for PDE-Electrical Analogy.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Sudeep Pasricha	A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Raguram Damodaran, Timothy Anderson, Sanjive Agarwala, Rama Venkatasubramanian, Michael Gill, Dhileep Gopalakrishnan, Anthony M. Hill, Abhijeet Chachad, Dheera Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, Shriram Moharil, Matthew Pierson, Steven Mullinnix, Hung Ong, David Thompson, Krishna Gurram, Oluleye Olorode, Nuruddin Mahmood, Jose Flores, Arjun Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman	A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Nitin Gupta, Tapas Nandy, Phalguni Bala	Self-Induced Supply Noise Reduction Technique in GBPS Rate Transmitters.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Nilanjan Chattaraj, Anindya Sundar Dhar	Random Access Analog Memory (RA2M) for Video Signal Application.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Sajib Kumar Mitra, Ahsan Raja Chowdhury	Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Tarun Kumar Agarwal, M. Jagadesh Kumar	Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	C. J. Janraj, T. Venkata Kalyan, Tripti Warrier, Madhu Mutyam	Way Sharing Set Associative Cache Architecture.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Lei Wang, Somnath Paul, Swarup Bhunia	Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Arvind Jain, Maheedhar Jalasutram, Srinivas Vooka, Prasun Nair, Neeraj Pradhan	At-speed Testing of Asynchronous Reset De-assertion Faults.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Himanshu Thapliyal, Nagarajan Ranganathan	Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Supriyo Maji, Pradip Mandal	A Fast Equation Free Iterative Approach to Analog Circuit Sizing.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Anindya Lal Roy, Anirban Bhattacharya, Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya	Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Vinayak Honkote, Ankit More, Baris Taskin	3-D Parasitic Modeling for Rotary Interconnects.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Angada B. Sachid, P. Paliwal, S. Joshi, M. Shojaei, D. Sharma, V. Ramgopal Rao	Circuit Optimization at 22nm Technology Node.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar	A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur	A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Bodhisatwa Mazumdar, Debdeep Mukhopadhyay, Indranil Sengupta	Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Subhajit Sen, Dan Babitch, Noshir Dubash	A Compact Temperature Sensor at 1.8µA per Hz Conversion Rate and 1.1 °C Accuracy for SOCs.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Hadi Hajimiri, Prabhat Mishra	Intra-Task Dynamic Cache Reconfiguration.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Jinpeng Lv, Priyank Kalla	Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Kameswara Rao B., Muralidhar Reddy B., Ravi Kishore B.	Tutorial T8B: Wireless System Design and Systems Engineering Challenges.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Saravana Kumar, Shouri Chatterjee	A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Jean-Michel Chabloz, Ahmed Hemani	Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy	Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Ritwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, Parthasarathi Dasgupta	A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Deepa N. Sarma, Gopalakrishnan Lakshminarayanan, K. V. R. Suryakiran Chavali	A Novel Encoding Scheme for Low Power in Network on Chip Links.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Cory E. Merkel, Dhireesha Kudithipudi	Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Debjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay	A Library for Passive Online Verification of Analog and Mixed-Signal Circuits.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Sathyam K. Pattanam, P. P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, Vikas Gautham, Raju Bala Showry Pudota	Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Annajirao Garimella, Punith R. Surkanti, Paul M. Furth	Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha	Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology.	VLSI Design	2012	DBLP DOI BibTeX RDF
2	Warin Sootkaneung, Kewal K. Saluja	Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate.	VLSI Design	2012	DBLP DOI BibTeX RDF