Search results for "Valentin Muresan"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Andrew Kinane, Valentin Muresan, Noel E. O'Connor	Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm.	EvoWorkshops	2006	DBLP DOI BibTeX RDF
1	Daniel Larkin, Andrew Kinane, Valentin Muresan, Noel E. O'Connor	An Efficient Hardware Architecture for a Neural Network Activation Function Generator.	ISNN	2006	DBLP DOI BibTeX RDF
1	Andrew Kinane, Valentin Muresan, Noel E. O'Connor	Towards an optimised VLSI design algorithm for the constant matrix multiplication problem.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Andrew Kinane, Alan Casey, Valentin Muresan, Noel E. O'Connor	FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator.	FPT	2005	DBLP BibTeX RDF
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	block-test scheduling, greedy algorithms, power constraints
1	Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow	Energy-Efficient Hardware Architecture for Variable N-point 1D DCT.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	A comparison of classical scheduling approaches in power-constrained block-test scheduling.	ITC	2000	DBLP DOI BibTeX RDF
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Power-Constrained Block-Test List Scheduling. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	Block-Test Scheduling, Tree-Growing Technique, Power Dissipation, List Scheduling
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints.	VTS	2000	DBLP DOI BibTeX RDF

Publications of "Valentin Muresan" ( http://dblp.L3S.de/Authors/Valentin_Muresan )