| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen |
A Reliable Routing Architecture and Algorithm for NoCs.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco |
CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco |
Approximating checkers for simulation acceleration. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco |
Gate-Level Simulation with GPU Computing. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph L. Greathouse, Chelsea LeBlanc, Todd M. Austin, Valeria Bertacco |
Highly scalable distributed dataflow analysis. |
CGO |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini |
A distributed and topology-agnostic approach for on-line NoC testing. |
NOCS |
2011 |
DBLP BibTeX RDF |
|
| 1 | Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco |
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment. |
PACT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ritesh Parikh, Valeria Bertacco |
Formally enhanced runtime verification to ensure NoC functional correctness. |
MICRO |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh |
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini |
ReliNoC: A reliable network for priority-based on-chip communication. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco |
Post-silicon bug diagnosis with inconsistent executions. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco |
Simulation-based signal selection for state restoration in silicon debug. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco |
Functional correctness for CMP interconnects. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko |
Logic synthesis and circuit customization using extensive external don't-cares. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rawan Abdel-Khalek, Valeria Bertacco |
SoCGuard: A runtime verification solution for the functional correctness of SoCs. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor |
Bridging pre-silicon verification and post-silicon validation. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
post-silicon, pre-silicon, verification, validation |
| 1 | Andrew DeOrio, Valeria Bertacco |
Electronic design automation for social networks. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
EDA algorithms, verification, social networks |
| 1 | Valeria Bertacco |
Post-silicon debugging for multi-core designs. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Pellegrini, Valeria Bertacco, Todd M. Austin |
Fault-based attack of RSA authentication. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Valeria Bertacco |
Verification Failures: What to Do When Things Go Wrong. |
Haifa Verification Conference |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Pellegrini, Valeria Bertacco |
Application-Aware diagnosis of runtime hardware faults. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Debapriya Chatterjee, Valeria Bertacco |
EQUIPE: Parallel equivalence checking with GP-GPUs. |
ICCD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco |
A Flexible Software-Based Framework for Online Detection of Hardware Defects. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen |
Inferno: Streamlining Verification With Inferred Semantics. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco |
Incremental Verification with Error Detection, Diagnosis, and Visualization. |
IEEE Design & Test of Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair |
|
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Debapriya Chatterjee, Valeria Bertacco |
Activity-based refinement for abstraction-guided simulation. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Hao, Valeria Bertacco |
PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew DeOrio, Valeria Bertacco |
Human computing for EDA. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
satisfiability, human computing |
| 1 | Valeria Bertacco |
Debugging strategies for mere mortals. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
validation, error correction, design verification, error diagnosis |
| 1 | David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester |
Vicis: a reliable network for unreliable silicon. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy |
| 1 | Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco |
Event-driven gate-level simulation with GP-GPUs. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
gate-level simulation, general purpose graphics processing unit (GP-GPU), high-performance simulation |
| 1 | Ilya Wagner, Valeria Bertacco |
Caspar: Hardware patching for multicore processors. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco |
GCS: High-performance gate-level simulation with GPGPUs. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw |
A highly resilient routing algorithm for fault-tolerant NoCs. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
Customizing IP cores for system-on-chip designs using extensive external don't-cares. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Andrew DeOrio, Ilya Wagner, Valeria Bertacco |
Dacota: Post-silicon validation of the memory subsystem in multi-core designs. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Fixing Design Errors With Counterexamples and Resynthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Wagner, Valeria Bertacco, Todd M. Austin |
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Plaza, Igor L. Markov, Valeria Bertacco |
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Automating Postsilicon Debugging and Repair. |
IEEE Computer |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao |
Reliable Systems on Unreliable Fabrics. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
SafeResynth: A new technique for physical synthesis. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Reap what you sow: spare cells for post-silicon metal fix. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Plaza, Igor L. Markov, Valeria Bertacco |
Optimizing non-monotonic interconnect using functional simulation and logic restructuring. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie |
Testudo: Heavyweight security analysis via statistical sampling. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Wagner, Valeria Bertacco |
MCjammer: Adaptive Verification for Multi-core Designs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Plaza, Igor L. Markov, Valeria Bertacco |
Random Stimulus Generation using Entropy and XOR Constraints. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Wagner, Valeria Bertacco |
Reversi: Post-silicon validation system for modern microprocessors. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew DeOrio, Adam Bauserman, Valeria Bertacco |
Post-silicon verification for cache coherence. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin |
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky |
Architecting a reliable CMP switch architecture. |
TACO |
2007 |
DBLP DOI BibTeX RDF |
CMP switch, reliability, defect-tolerance |
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Postplacement rewiring by exhaustive search for functional symmetries. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
VLSI, placement, rewiring |
| 1 | Ilya Wagner, Valeria Bertacco, Todd M. Austin |
Microprocessor Verification via Feedback-Adjusted Markov Models. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
Simulation-Based Bug Trace Minimization With BMC-Based Refinement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco |
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco |
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Fixing Design Errors with Counterexamples and Resynthesis. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking |
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Safe Delay Optimization for Physical Synthesis. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay |
| 1 | Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Node Mergers in the Presence of Don't Cares. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin |
Low-cost protection for SER upsets and silicon defects. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Wagner, Valeria Bertacco |
Engineering trust with semantic guardians. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew DeOrio, Adam Bauserman, Valeria Bertacco |
Chico: An On-chip Hardware Checker for Pipeline Control Logic. |
MTV |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Automating post-silicon debugging and repair. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Valeria Bertacco |
Scalable Hardware Verification with Symbolic Simulation. |
|
2006 |
DOI RDF |
|
| 1 | Valeria Bertacco |
Formal verification for real-world designs. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Valeria Bertacco |
Low maintenance verification. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin |
Ultra low-cost defect protection for microprocessor pipelines. |
ASPLOS |
2006 |
DBLP DOI BibTeX RDF |
defect-protection, reliability, pipelines, low-cost |
| 1 | Ilya Wagner, Valeria Bertacco, Todd M. Austin |
Shielding against design flaws with field repairable control logic. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
hardware patching, processor verification |
| 1 | Ilya Wagner, Valeria Bertacco, Todd M. Austin |
Depth-driven verification of simultaneous interfaces. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Smitha Shyam, Valeria Bertacco |
Distance-guided hybrid verification with GUIDO. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang 0011, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky |
BulletProof: a defect-tolerant CMP switch architecture. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Beth Isaksen, Valeria Bertacco |
Verification through the principle of least astonishment. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilya Wagner, Valeria Bertacco, Todd M. Austin |
StressTest: an automatic approach to test generation via activity monitors. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
directed-random simulation, architectural simulation, high-performance simulation |
| 1 | Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge |
Opportunities and challenges for better than worst-case design. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Plaza, Valeria Bertacco |
STACCATO: disjoint support decompositions from BDDs through symbolic kernels. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
Simulation-based bug trace minimization with BMC-based refinement. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Todd M. Austin, Valeria Bertacco |
Deployment of Better Than Worst-Case Design: Solutions and Needs. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge |
Microarchitectural power modeling techniques for deep sub-micron microprocessors. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
power modeling, deep sub-micron |
| 1 | Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge |
Circuit-aware architectural simulation. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
circuit simulation, architectural simulation, high-performance simulation, computer system simulation |
| 1 | Valeria Bertacco, Kunle Olukotun |
Efficient state representation for symbolic simulation. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
formal verification, BDDs, symbolic simulation |
| 1 | Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long |
Smart Simulation Using Collaborative Formal and Simulation Engines. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Valeria Bertacco, Maurizio Damiani, Stefano Quer |
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Valeria Bertacco, Maurizio Damiani |
The disjunctive decomposition of logic functions. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
disjunctive decomposition, combinational logic optimization |
| 1 | Valeria Bertacco, Maurizio Damiani |
Boolean Function Representation Using Parallel-Access Diagrams. (PDF / PS) |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Valeria Bertacco, Maurizio Damiani |
Boolean Function Representation Based on Disjoint-Support Decompositions. (PDF / PS) |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
|
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