Search results for "Vasilis F. Pavlidis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli	Inter-Plane Communication Methods for 3-D ICs.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris	A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric.	TRETS	2012	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli	The combined effect of process variations and power supply noise on clock skew and jitter.	ISQED	2012	DBLP DOI BibTeX RDF
1	Cheng Zhang, Vasilis F. Pavlidis, Giovanni De Micheli	Voltage propagation method for 3-D power grid analysis.	DATE	2012	DBLP BibTeX RDF
1	Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman	Clock Distribution Networks in 3-D Integrated Systems.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli	Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Analytical heat transfer model for thermal through-silicon vias.	DATE	2011	DBLP BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Skew variability in 3-D ICs with multiple clock domains.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman	Clock distribution models of 3-D integrated systems.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Process-induced skew variation for scaled 2-D and 3-D ICs.	SLIP	2010	DBLP DOI BibTeX RDF
1	Ioannis Tsioutsios, Vasilis F. Pavlidis, Giovanni De Micheli	Physical design tradeoffs in power distribution networks for 3-D ICs.	ICECS	2010	DBLP DOI BibTeX RDF
1	Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli	Performance analysis of 3-D monolithic integrated circuits.	3DIC	2010	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Giovanni De Micheli	Power distribution paths in 3-D ICS.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	power distribution network, 3-D ICS, 3-D integration, through silicon vias
1	Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris	A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs.	DATE	2009	DBLP BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.	NanoNet	2009	DBLP DOI BibTeX RDF	timing optimization, on-chip interconnect, repeater insertion, 3-D ICs
1	Vasilis F. Pavlidis, Eby G. Friedman	Timing-driven via placement heuristics for three-dimensional ICs.	Integration	2008	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	3-D Topologies for Networks-on-Chip.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris	Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.	FPL	2007	DBLP DOI BibTeX RDF
1	Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris	A software-supported methodology for designing high-performance 3D FPGA architectures.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	Via placement for minimum interconnect delay in three-dimensional (3D) circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	Interconnect delay minimization through interlayer via placement in 3-D ICs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	RC interconnects, elmore delay, 3-D ICs
1	Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis	A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.	ISCAS	2003	DBLP DOI BibTeX RDF

Publications of "Vasilis F. Pavlidis" ( http://dblp.L3S.de/Authors/Vasilis_F._Pavlidis )