Search results for "Vector instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Chris R. Jesshope	Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines.	ACSAC	2001	DBLP DOI BibTeX RDF
2	James E. Smith, Greg Faanes, Rabin A. Sugumar	Vector instruction set support for conditional operations.	ISCA	2000	DBLP DOI BibTeX RDF
1	Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang 0001, Bin Liu 0006, Raghu Prabhakar, Glenn Reinman, Marco Vitanza	Compilation and architecture support for customized vector instruction extension.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan	StVEC: A Vector Instruction Extension for High Performance Stencil Computation.	PACT	2011	DBLP DOI BibTeX RDF
1	Rajkishore Barik, Jisheng Zhao, Vivek Sarkar	Automatic vector instruction selection for dynamic compilation.	PACT	2010	DBLP DOI BibTeX RDF
1	Diego F. Aranha, Julio López, Darrel Hankerson	Efficient Software Implementation of Binary Field Arithmetic Using Vector Instruction Sets.	LATINCRYPT	2010	DBLP DOI BibTeX RDF
1	Xavier Llorà, Anusha Priya, Rohit Bhargava	Observer-invariant histopathology using genetics-based machine learning.	Natural Computing	2009	DBLP DOI BibTeX RDF	Observer-invariant histopathology, Vector instruction, MPI, Learning Classifier Systems, Hardware acceleration, Massive parallelism, Genetics-based machine learning, SSE2
1	Drew Mellor, Steven P. Nicklin	A population-based approach to finding the matchset of a learning classifier system efficiently.	GECCO	2009	DBLP DOI BibTeX RDF	efficient matching, learning classifier systems, xcs, lcs
1	Markus Püschel	Automatic synthesis of high performance mathematical programs.	ISSAC	2009	DBLP DOI BibTeX RDF	parallelization, domain-specific language, automation, vectorization, high performance, fourier transform, matrix algebra, rewriting, program generation
1	Anna Inn-Tung Chen, Ming-Shing Chen, Tien-Ren Chen, Chen-Mou Cheng, Jintai Ding, Eric Li-Hsiang Kuo, Frost Yu-Shuang Lee, Bo-Yin Yang	SSE Implementation of Multivariate PKCs on Modern x86 CPUs.	CHES	2009	DBLP DOI BibTeX RDF	multivariate public key cryptosystem (MPKC), ?IC, vector instructions, SSSE3, Wiedemann, TTS, rainbow, SSE2
1	Kevin Williams, Albert Noll, Andreas Gal, David Gregg	Optimization strategies for a java virtual machine interpreter on the cell broadband engine.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	java, virtual machine, interpreter, language implementation
1	Robert L. Bocchino Jr., Vikram S. Adve	Vector LLVA: a virtual vector instruction set for media processing.	VEE	2006	DBLP DOI BibTeX RDF	virtual instruction sets, multimedia, SIMD, vector
1	Xavier Llorà, Kumara Sastry	Fast rule matching for learning classifier systems via vector instructions.	GECCO	2006	DBLP DOI BibTeX RDF	fast rule matching, learning classifier systems, Altivec, vector operations, SSE2
1	Qingda Lu, Sriram Krishnamoorthy, P. Sadayappan	Combining analytical and empirical approaches in tuning matrix transposition.	PACT	2006	DBLP DOI BibTeX RDF	bandwidth-limited, empirical search, SIMD, tiling, spatial locality, conflict misses, matrix transposition
1	Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado, Francky Catthoor	Improving superword level parallelism support in modern compilers.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	superword level parallelism, FIR, automatic vectorization
1	Ahmed El-Mahdy, Ian Watson	A Two Dimensional Vector Architecture for Multimedia.	Euro-Par	2001	DBLP DOI BibTeX RDF
1	Stamatis Vassiliadis, Edwin A. Hakkennes, J. S. S. M. Wong, Gerald G. Pechanek	The Sum-Absolute-Difference Motion Estimation Accelerato.	EUROMICRO	1998	DBLP DOI BibTeX RDF
1	Takashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura	A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
1	V. Prasad Krothapalli, P. Sadayappan	Exploiting Parallelism Through Run-Time Analysis on a Vector Processor (Abstract).	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF	FORTRAN
1	Hideo Wada, Koichi Ishii, Shigeko Yazawa, Shun Kawabe	High-Speed Vector Instruction Execution Schemes of HITACHI Supercomputer S-820 System.	ICPP	1988	DBLP BibTeX RDF
1	Christine Eisenbeis, William Jalby, Alain Lichnewsky	Squeezing more CPU performance out of a Cray-2 by Vector block scheduling.	SC	1988	DBLP BibTeX RDF
1	Brian B. Moore, Andris Padegs, Ronald M. Smith, Werner Buchholz	Concepts of the System/370 Vector Architecture.	ISCA	1987	DBLP DOI BibTeX RDF