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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 37 occurrences of 31 keywords
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Results
Found 24 publication records. Showing 24 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Rajeev Balasubramonian, Vijayalakshmi Srinivasan (eds.) |
2012 IEEE International Symposium on Performance Analysis of Systems & Software, New Brunswick, NJ, USA, April 1-3, 2012  |
ISPASS  |
2012 |
DBLP BibTeX RDF |
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| 1 | Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan |
Efficient scrub mechanisms for error-prone emerging memories.  |
HPCA  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Andrew B. Kahng, Vijayalakshmi Srinivasan |
Big Chips.  |
IEEE Micro  |
2011 |
DBLP DOI BibTeX RDF |
Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis |
| 1 | Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas, Vijayalakshmi Srinivasan |
SPATL: Honey, I Shrunk the Coherence Directory.  |
PACT  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee |
SAFER: Stuck-At-Fault Error Recovery for Memories.  |
MICRO  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers |
Scalable high performance main memory system using phase-change memory technology.  |
ISCA  |
2009 |
DBLP DOI BibTeX RDF |
dram caching, phase change memory, wear leveling |
| 1 | Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos |
A tagless coherence directory.  |
MICRO  |
2009 |
DBLP DOI BibTeX RDF |
directory coherence, cache coherence, Bloom filters |
| 1 | Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis Lastras, Bülent Abali |
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling.  |
MICRO  |
2009 |
DBLP DOI BibTeX RDF |
phase change memory, wear leveling, endurance |
| 1 | Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan, Jim Mitchell |
An analysis of the effects of miss clustering on the cost of a cache miss.  |
Conf. Computing Frontiers  |
2007 |
DBLP DOI BibTeX RDF |
algorithm, cache, pipeline, spectrogram |
| 1 | Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan, Arthur Nadas |
Pipeline spectroscopy.  |
Experimental Computer Science  |
2007 |
DBLP DOI BibTeX RDF |
cost of a miss, probability transition matrix, cache, convex combination |
| 1 | Thomas R. Puzak, Allan Hartstein, Viji Srinivasan, Philip G. Emma, Arthur Nadas |
Pipeline spectroscopy.  |
SIGMETRICS  |
2007 |
DBLP DOI BibTeX RDF |
cost of a miss, probability transition matrix, cache, convex combination |
| 1 | Allan Hartstein, Viji Srinivasan, Thomas R. Puzak, Philip G. Emma |
Cache miss behavior: is it sqrt(2)?  |
Conf. Computing Frontiers  |
2006 |
DBLP DOI BibTeX RDF |
performance, memory hierarchy, cache organization |
| 1 | Philip G. Emma, Allan Hartstein, Thomas R. Puzak, Viji Srinivasan |
Exploring the limits of prefetching.  |
IBM Journal of Research and Development  |
2005 |
DBLP BibTeX RDF |
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| 1 | Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan |
When prefetching improves/degrades performance.  |
Conf. Computing Frontiers  |
2005 |
DBLP DOI BibTeX RDF |
prefetching algorithm, cache, prefetch, coverage, accuracy, timeliness |
| 1 | Viji Srinivasan, Edward S. Davidson, Gary S. Tyson |
A Prefetch Taxonomy.  |
IEEE Trans. Computers  |
2004 |
DBLP DOI BibTeX RDF |
Prefetch algorithms, cache memory systems |
| 1 | Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma |
Integrated Analysis of Power and Performance for Pipelined Microprocessors.  |
IEEE Trans. Computers  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose |
Microarchitectural techniques for power gating of execution units.  |
ISLPED  |
2004 |
DBLP DOI BibTeX RDF |
execution units, low power, microarchitecture, power-gating |
| 1 | David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield |
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.  |
IBM Journal of Research and Development  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu |
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.  |
PACS  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma |
Optimizing pipelines for power and performance.  |
MICRO  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas |
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.  |
PACS  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak |
Branch History Guided Instruction Prefetching.  |
HPCA  |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson |
Active Management of Data Caches by Exploiting Reuse Information.  |
IEEE Trans. Computers  |
1999 |
DBLP DOI BibTeX RDF |
Multilateral cache, reuse information, active management |
| 1 | Sucheta Chodnekar, Viji Srinivasan, Aniruddha S. Vaidya, Anand Sivasubramaniam, Chita R. Das |
Towards a Communication Characterization Methodology for Parallel Applications.  |
HPCA  |
1997 |
DBLP DOI BibTeX RDF |
Communication characterization, Performance Evaluation, Interconnection networks, Parallel applications, Execution driven simulation |
Displaying result #1 - #24 of 24 (100 per page; Change: )
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