Search results for "Vijaykrishnan Narayanan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jing Xie, Vijaykrishnan Narayanan, Yuan Xie	Mitigating electromigration of power supply networks using bidirectional current stress.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan	A reconfigurable platform for the design and verification of domain-specific accelerators.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jagdish Sabarad, Srinidhi Kestur, Sun-Mi Park, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla	A reconfigurable accelerator for neuromorphic object recognition.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan	When to forget: A system-level perspective on STT-RAMs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Sun-Mi Park, Srinidhi Kestur, Jagdish Sabarad, Vijaykrishnan Narayanan, Mary Jane Irwin	An FPGA-based accelerator for cortical object classification.	DATE	2012	DBLP BibTeX RDF
1	Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis	Hazard driven test generation for SMT processors.	DATE	2012	DBLP BibTeX RDF
1	Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das	RAFT: A router architecture with frequency tuning for on-chip networks.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-Aware Task and Communication Mapping for MPSoC Architecture.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	A case for heterogeneous on-chip interconnects for CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Chi-Li Yu, Jungsub Kim, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti	FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Chi-Li Yu, Kevin M. Irick, Chaitali Chakrabarti, Vijaykrishnan Narayanan	Multidimensional DFT IP Generator for FPGA Platforms.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan Narayanan	Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA.	FPL	2011	DBLP DOI BibTeX RDF	fpga, primary visual cortex, gabor
1	Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan	Impact of Circuit Degradation on FPGA Design Security.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan	Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Ahmed Al-Maashri, Michael DeBole, C.-L. Yu, Vijaykrishnan Narayanan, Chaitali Chakrabarti	A hardware architecture for accelerating neuromorphic vision algorithms.	SiPS	2011	DBLP DOI BibTeX RDF
1	Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta	Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores.	ISLPED	2011	DBLP BibTeX RDF
1	Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta	Enabling architectural innovations using non-volatile memory.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan	Automated mapping for reconfigurable single-electron transistor arrays.	DAC	2011	DBLP DOI BibTeX RDF
1	Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan	An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.	DAC	2011	DBLP DOI BibTeX RDF
1	Srinidhi Kestur, Kevin M. Irick, Sungho Park, Ahmed Al-Maashri, Vijaykrishnan Narayanan, Chaitali Chakrabarti	An algorithm-architecture co-design framework for gridding reconstruction using FPGAs.	DAC	2011	DBLP DOI BibTeX RDF
1	Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan	An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization.	FCCM	2011	DBLP DOI BibTeX RDF
1	Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan	A streaming FPGA implementation of a steerable filter for real-time applications (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan	SHARC: A streaming model for FPGA accelerators and its application to Saliency.	DATE	2011	DBLP DOI BibTeX RDF
1	Michael DeBole, Ahmed Al-Maashri, M. Cotter, C.-L. Yu, Chaitali Chakrabarti, Vijaykrishnan Narayanan	A framework for accelerating neuromorphic-vision algorithms on FPGAs.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Total Power Optimization for Combinational Logic Using Genetic Algorithms.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Sungmin Bae, Narayanan Vijaykrishnan	Thermal Gradient Aware Clock Skew Scheduling for FPGAs.	FPL	2010	DBLP DOI BibTeX RDF
1	Vikram Sampath Kumar, Kevin M. Irick, Ahmed Al-Maashri, Narayanan Vijaykrishnan	A Scalable Bandwidth Aware Architecture for Connected Component Labeling.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	J. Singh, Krishnan Ramakrishnan, S. Mookerjea, Suman Datta, Narayanan Vijaykrishnan, D. K. Pradhan	A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Aditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan	A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching.	DATE	2010	DBLP BibTeX RDF
1	Andrew J. Ricketts, J. Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, D. K. Pradhan	Investigating the impact of NBTI on different power saving cache strategies.	DATE	2010	DBLP BibTeX RDF
1	Chrysostomos Nicopoulos, Suresh Srinivasan, Aditya Yanamandra, Dongkook Park, Vijaykrishnan Narayanan, Chita R. Das, Mary Jane Irwin	On the Effects of Process Variation in Network-on-Chip Architectures.	IEEE Trans. Dependable Sec. Comput.	2010	DBLP DOI BibTeX RDF
1	Vinay Saripalli, Lu Liu, Suman Datta, Vijaykrishnan Narayanan	Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das	Network-on-Chip Architectures - A Holistic Design Exploration		2010	DBLP DOI BibTeX RDF
1	Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vijaykrishnan Narayanan	Bandwidth-intensive FPGA architecture for multi-dimensional DFT.	ICASSP	2010	DBLP DOI BibTeX RDF
1	Vijaykrishnan Narayanan, Ahmed Al-Maashri, Kevin M. Irick, Michael DeBole, Sungho Park	AutoFLEX: A Framework for Image Processing Applications on Multiple-FPGA Systems.	ERSA	2010	DBLP BibTeX RDF
1	Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan	Optimizing power and performance for reliable on-chip networks.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Srinidhi Kestur, Sungho Park, Kevin M. Irick, Vijaykrishnan Narayanan	Accelerating the Nonuniform Fast Fourier Transform Using FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta	Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.	VLSI Design	2010	DBLP DOI BibTeX RDF	Single Electron Transistor, Energy-Delay Trade-Off, Energy Efficient
1	Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan	New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.	International Journal of Parallel Programming	2009	DBLP DOI BibTeX RDF
1	Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Compiler-assisted soft error detection under performance and energy constraints in embedded systems.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	instruction duplication, reliability, Embedded systems, compilers, energy consumption, soft errors
1	Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies.	IJDSN	2009	DBLP DOI BibTeX RDF
1	Sungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan	A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das	A case for dynamic frequency tuning in on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF
1	Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan	A framework for estimating NBTI degradation of microarchitectural components.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan	Exploiting clock skew scheduling for FPGA.	DATE	2009	DBLP BibTeX RDF
1	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu	Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Jungsub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin M. Irick, Kanwaldeep Sobti, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun	An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Madhu Mutyam, Feng Wang 0004, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin	Process-Variation-Aware Adaptive Cache Architecture and Management.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Tamer Ragheb, Andrew J. Ricketts, Mosin Mondal, Sami Kirolos, Greg M. Link, Vijaykrishnan Narayanan, Yehia Massoud	Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Prasanth Mangalagiri, Vijaykrishnan Narayanan	Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Jungsub Kim, Chi-Li Yu, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti	FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data.	SiPS	2009	DBLP DOI BibTeX RDF
1	Suman Datta, Vijaykrishnan Narayanan	Green transistors to green architectures.	ISLPED	2009	DBLP DOI BibTeX RDF	performance, design, transistor
1	Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan	A criticality-driven microarchitectural three dimensional (3D) floorplanner.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel	Security and Dependability of Embedded Systems: A Computer Architects' Perspective.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta	Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.	NanoNet	2009	DBLP DOI BibTeX RDF	low-energy circuits, single electron transistors, binary decision diagram logic circuits
1	Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan	Test Generation for Precise Interrupts on Out-of-Order Microprocessors.	MTV	2009	DBLP DOI BibTeX RDF
1	Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan	In-Network Caching for Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Suresh Srinivasan, Lin Li, Martino Ruggiero, Federico Angiolini, Narayanan Vijaykrishnan, Luca Benini	Exploring architectural solutions for energy optimisations in bus-based system-on-chip.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Yuh-Fang Tsai, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	Design Space Exploration for 3-D Cache.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman	Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie	Case Study of Reliability-Aware and Low-Power Design.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu	Hierarchical Soft Error Estimation Tool (HSEET).	ISQED	2008	DBLP DOI BibTeX RDF	Reliability, Soft Errors, Flip-Flop, Combinational Logic
1	Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das	MIRA: A Multi-layered On-Chip Interconnect Router Architecture.	ISCA	2008	DBLP DOI BibTeX RDF
1	Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam	Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin	Analysis and solutions to issue queue process variation.	DSN	2008	DBLP DOI BibTeX RDF
1	Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie	Comparative analysis of NBTI effects on low power and high performance flip-flops.	ICCD	2008	DBLP DOI BibTeX RDF
1	Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari	Toward Increasing FPGA Lifetime.	IEEE Trans. Dependable Sec. Comput.	2008	DBLP DOI BibTeX RDF	Reliability, Reconfigurable hardware, availability and serviceability
1	Vijaykrishnan Narayanan	Editorial.	JETC	2008	DBLP DOI BibTeX RDF
1	Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijaykrishnan Narayanan	Efficient image reconstruction using partial 2D Fourier transform.	SiPS	2008	DBLP DOI BibTeX RDF
1	Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle (eds.)	Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008	ISLPED	2008	DBLP BibTeX RDF
1	Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim	A low-power phase change memory based hybrid cache architecture.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	PRAM, phase change memory
1	Vijaykrishnan Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja (eds.)	Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008	ACM Great Lakes Symposium on VLSI	2008	DBLP BibTeX RDF
1	David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijaykrishnan Narayanan	Reliability-aware design for nanometer-scale devices.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen	A Hardware Efficient Support Vector Machine Architecture for FPGA.	FCCM	2008	DBLP DOI BibTeX RDF
1	Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das	Performance and power optimization through data compression in Network-on-Chip architectures.	HPCA	2008	DBLP DOI BibTeX RDF
1	Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan	Thermal-aware reliability analysis for platform FPGAs.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin	Reducing non-deterministic loads in low-power caches via early cache set resolution.	Microprocessors and Microsystems	2007	DBLP DOI BibTeX RDF
1	Aman Gayasen, Suresh Srinivasan, Narayanan Vijaykrishnan, Mahmut T. Kandemir	Design of power-aware FPGA fabrics.	IJES	2007	DBLP DOI BibTeX RDF
1	Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio	OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	branch prediction, processor architectures, Pipeline processors, performance of systems, hardware/software interfaces, computer system implementation
1	Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Thermal-Aware Task Allocation and Scheduling for Embedded Systems	CoRR	2007	DBLP BibTeX RDF
1	Greg M. Link, Narayanan Vijaykrishnan	Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip	CoRR	2007	DBLP BibTeX RDF
1	Feng Wang 0004, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	On-chip bus thermal analysis and optimisation.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir	Optimising power efficiency in trace cache fetch unit.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir	On the Detection of Clones in Sensor Networks Using Random Key Predistribution.	IEEE Transactions on Systems, Man, and Cybernetics, Part C	2007	DBLP DOI BibTeX RDF
1	Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Reliability-aware Co-synthesis for Embedded Systems.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	design methodology, scheduling algorithm, embedded system design
1	Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin	Variation Impact on SER of Combinational Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
1	Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud	Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers.	ISQED	2007	DBLP DOI BibTeX RDF
1	Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin	Variation Analysis of CAM Cells.	ISQED	2007	DBLP DOI BibTeX RDF
1	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	A novel dimensionally-decomposed router for on-chip communication in 3D architectures.	ISCA	2007	DBLP DOI BibTeX RDF	3D architecture, 3D integration, network-on-chip (NoC)
1	Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud	Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin	Investigating Simple Low Latency Reliable Multiported Register Files.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin	Impact of NBTI on FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	Architecting Microprocessor Components in 3D Design Space.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Madhu Mutyam, Narayanan Vijaykrishnan	Working with process variation aware caches.	DATE	2007	DBLP DOI BibTeX RDF
1	Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud	Assessing carbon nanotube bundle interconnect for future FPGA architectures.	DATE	2007	DBLP DOI BibTeX RDF
1	Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud	Thermally robust clocking schemes for 3D integrated circuits.	DATE	2007	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-aware task allocation and scheduling for MPSoC.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan	FPGA routing architecture analysis under variations.	ICCD	2007	DBLP DOI BibTeX RDF

Publications of Vijaykrishnan Narayanan Narayanan Vijaykrishnan ( http://dblp.L3S.de/Authors/Vijaykrishnan_Narayanan )