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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 5 occurrences of 4 keywords
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Results
Found 24 publication records. Showing 24 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang |
Circuit-level delay modeling considering both TDDB and NBTI.  |
ISQED  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester |
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.  |
ISLPED  |
2011 |
DBLP BibTeX RDF |
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| 1 | Tibor Bosse, Vikas Chandra, Eve Mitleton-Kelly, C. Natalie van der Wal |
Analysis of Beliefs of Survivors of the 7/7 London Bombings: Application of a Formal Model for Contagion of Mental States.  |
ICONIP  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Robert C. Aitken |
On the impact of gate oxide degradation on SRAM dynamic and static write-ability.  |
ASP-DAC  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun |
Dynamic write limited minimum operating voltage for nanoscale SRAMs.  |
DATE  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Robert C. Aitken |
Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown.  |
DATE  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Satyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun |
Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.  |
ISQED  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken |
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs.  |
DATE  |
2010 |
DBLP BibTeX RDF |
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| 1 | Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken |
TIMBER: Time borrowing and error relaying for online timing error resilience.  |
DATE  |
2010 |
DBLP BibTeX RDF |
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| 1 | Michael Wieckowski, Dennis Sylvester, David Blaauw, Vikas Chandra, Sachin Idgunji, Cezary Pietrzyk, Robert C. Aitken |
A black box method for stability analysis of arbitrary SRAM cell structures.  |
DATE  |
2010 |
DBLP BibTeX RDF |
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| 1 | Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken |
Analytical model for TDDB-based performance degradation in combinational logic.  |
DATE  |
2010 |
DBLP BibTeX RDF |
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| 1 | Vikas Chandra, Tom Andre |
Memory trends.  |
CICC  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Saurabh K. Tiwary, Amith Singhee, Vikas Chandra |
Robust Circuit Design: Challenges and Solutions.  |
VLSI Design  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Robert C. Aitken |
Impact of voltage scaling on nanoscale SRAM reliability.  |
DATE  |
2009 |
DBLP BibTeX RDF |
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| 1 | Vikas Chandra |
Designing dependable multicore system with unreliable components.  |
IOLTS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Robert C. Aitken |
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.  |
DFT  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Herman Schmit, Vikas Chandra |
Layout techniques for FPGA switch blocks.  |
IEEE Trans. VLSI Syst.  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Anthony Xu, Herman Schmit |
A low power approach to system level pipelined interconnect design.  |
SLIP  |
2004 |
DBLP DOI BibTeX RDF |
pipelined interconnect, low power, voltage scaling |
| 1 | Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi |
An Interconnect Channel Design Methodology for High Performance Integrated Circuits.  |
DATE  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi |
A power aware system level interconnect design methodology for latency-insensitive systems.  |
ICCAD  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit |
Heterogeneous Programmable Logic Block Architectures.  |
DATE  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns |
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.  |
ICCD  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Vikas Chandra, Herman Schmit |
Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach.  |
ISVLSI  |
2002 |
DBLP DOI BibTeX RDF |
FPGA Interconnect |
| 1 | Herman Schmit, Vikas Chandra |
FPGA switch block layout and evaluation.  |
FPGA  |
2002 |
DBLP DOI BibTeX RDF |
VLSI layout, FPGA interconnect |
Displaying result #1 - #24 of 24 (100 per page; Change: )
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