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Publications of "Vikas Chandra" ( http://dblp.L3S.de/Authors/Vikas_Chandra )

  Author page on DBLP  Author page in RDF  Community of Vikas Chandra in ASPL-2

Publication years (Num. hits)
2002-2010 (18) 2011 (6)
Publication types (Num. hits)
article(1) inproceedings(23)
Venues (Conferences, Journals, ...)
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The graphs summarize 5 occurrences of 4 keywords

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Found 24 publication records. Showing 24 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang Circuit-level delay modeling considering both TDDB and NBTI. Search on Bibsonomy ISQED The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs. Search on Bibsonomy ISLPED The full citation details ... 2011 DBLP  BibTeX  RDF
1Tibor Bosse, Vikas Chandra, Eve Mitleton-Kelly, C. Natalie van der Wal Analysis of Beliefs of Survivors of the 7/7 London Bombings: Application of a Formal Model for Contagion of Mental States. Search on Bibsonomy ICONIP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Robert C. Aitken On the impact of gate oxide degradation on SRAM dynamic and static write-ability. Search on Bibsonomy ASP-DAC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun Dynamic write limited minimum operating voltage for nanoscale SRAMs. Search on Bibsonomy DATE The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Robert C. Aitken Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown. Search on Bibsonomy DATE The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Satyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation. Search on Bibsonomy ISQED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken On the efficacy of write-assist techniques in low voltage nanoscale SRAMs. Search on Bibsonomy DATE The full citation details ... 2010 DBLP  BibTeX  RDF
1Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken TIMBER: Time borrowing and error relaying for online timing error resilience. Search on Bibsonomy DATE The full citation details ... 2010 DBLP  BibTeX  RDF
1Michael Wieckowski, Dennis Sylvester, David Blaauw, Vikas Chandra, Sachin Idgunji, Cezary Pietrzyk, Robert C. Aitken A black box method for stability analysis of arbitrary SRAM cell structures. Search on Bibsonomy DATE The full citation details ... 2010 DBLP  BibTeX  RDF
1Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken Analytical model for TDDB-based performance degradation in combinational logic. Search on Bibsonomy DATE The full citation details ... 2010 DBLP  BibTeX  RDF
1Vikas Chandra, Tom Andre Memory trends. Search on Bibsonomy CICC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Saurabh K. Tiwary, Amith Singhee, Vikas Chandra Robust Circuit Design: Challenges and Solutions. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Robert C. Aitken Impact of voltage scaling on nanoscale SRAM reliability. Search on Bibsonomy DATE The full citation details ... 2009 DBLP  BibTeX  RDF
1Vikas Chandra Designing dependable multicore system with unreliable components. Search on Bibsonomy IOLTS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Robert C. Aitken Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Herman Schmit, Vikas Chandra Layout techniques for FPGA switch blocks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Anthony Xu, Herman Schmit A low power approach to system level pipelined interconnect design. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF pipelined interconnect, low power, voltage scaling
1Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi An Interconnect Channel Design Methodology for High Performance Integrated Circuits. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi A power aware system level interconnect design methodology for latency-insensitive systems. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit Heterogeneous Programmable Logic Block Architectures. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
1Vikas Chandra, Herman Schmit Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA Interconnect
1Herman Schmit, Vikas Chandra FPGA switch block layout and evaluation. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF VLSI layout, FPGA interconnect
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