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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 4 publication records. Showing 4 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda |
500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti".  |
ISVLSI  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa |
Extraction of Aspect Ratio for Non-Manhattan CMOS Devices. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Balaji Srinivasan, Vinay Bhaskar Chandratre |
An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Delay Lock Loop |
| 1 | Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani |
0.35ยต, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
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