|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1 occurrences of 1 keywords
|
|
|
|
|
Results
Found 6 publication records. Showing 6 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta |
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores.  |
ISLPED  |
2011 |
DBLP BibTeX RDF |
|
| 1 | Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta |
Enabling architectural innovations using non-volatile memory.  |
ACM Great Lakes Symposium on VLSI  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan |
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.  |
DAC  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Saripalli, Lu Liu, Suman Datta, Vijaykrishnan Narayanan |
Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits.  |
J. Low Power Electronics  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta |
Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.  |
VLSI Design  |
2010 |
DBLP DOI BibTeX RDF |
Single Electron Transistor, Energy-Delay Trade-Off, Energy Efficient |
| 1 | Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta |
Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.  |
NanoNet  |
2009 |
DBLP DOI BibTeX RDF |
low-energy circuits, single electron transistors, binary decision diagram logic circuits |
Displaying result #1 - #6 of 6 (100 per page; Change: )
|
|