| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Vishwani D. Agrawal |
Editorial.  |
J. Electronic Testing  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Ashfaq Shukoor, Vishwani D. Agrawal |
Diagnostic Test Set Minimization and Full-Response Fault Dictionary. |
J. Electronic Testing |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal, Srimat T. Chakradhar (eds.) |
25th International Conference on VLSI Design, VLSID 2012, Hyderabad, India, January 7-11, 2012 |
VLSI Design |
2012 |
DBLP BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Keynote Talk: A History of the VLSI Design Conference. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyadharshini Shanmugasundaram, Vishwani D. Agrawal |
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. |
VLSI Design |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyungseok Kim, Vishwani D. Agrawal |
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. |
J. Low Power Electronics |
2011 |
DBLP BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyungseok Kim, Vishwani D. Agrawal |
Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Suraj Sindia, Vishwani D. Agrawal, Virendra Singh |
Test and Diagnosis of Analog Circuits Using Moment Generating Functions. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyadharshini Shanmugasundaram, Vishwani D. Agrawal |
Dynamic scan clock control for test time reduction maintaining peak power limit. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Suraj Sindia, Vishwani D. Agrawal, Virendra Singh |
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyungseok Kim, Vishwani D. Agrawal |
True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhang, Vishwani D. Agrawal |
Reduced complexity test generation algorithms for transition fault diagnosis. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
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| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Wang, Vishwani D. Agrawal |
Soft error rate determination for nanoscale sequential logic. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhang, Vishwani D. Agrawal |
A diagnostic test generation system. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhang, Vishwani D. Agrawal |
A diagnostic test generation system and a coverage metric. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nitin Yogi, Vishwani D. Agrawal |
Application of signal and noise theory to digital VLSI testing. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Suraj Sindia, Virendra Singh, Vishwani D. Agrawal |
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
polynomial coefficients, fault diagnosis, sensitivity, nonlinear circuits |
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Variable Input Delay CMOS Logic for Low Power Design. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2009 |
DBLP BibTeX RDF |
|
| 1 | Jins D. Alexander, Vishwani D. Agrawal |
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Suraj Sindia, Virendra Singh, Vishwani D. Agrawal |
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Suraj Sindia, Virendra Singh, Vishwani D. Agrawal |
Polynomial coefficient based DC testing of non-linear analog circuits. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
DC test, non-linear circuit test, polynomial, curve fitting, parametric faults |
| 1 | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal |
On Minimization of Peak Power for Scan Circuit during Test. |
European Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
Power droop, Test vector re-ordering, Low power test, Peak Power |
| 1 | Mohammed Ashfaq Shukoor, Vishwani D. Agrawal |
A Two Phase Approach for Minimal Diagnostic Test Set Generation. |
European Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
generalized fault independence, Fault diagnosis, integer linear programming, fault dictionary, test minimization |
| 1 | Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal |
Output Hazard-Free Transition Delay Fault Test Generation. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Wang, Vishwani D. Agrawal |
Soft Error Rates with Inertial and Logical Masking. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Jiang, Vishwani D. Agrawal |
Designing Variation-tolerance in Mixed-signal Components of a System-on-chip. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Jiang, Vishwani D. Agrawal |
Built-in Self-Calibration of On-chip DAC and ADC. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
A tutorial on test power. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal |
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph |
| 1 | Yuanlin Lu, Vishwani D. Agrawal |
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Wang, Vishwani D. Agrawal |
Single Event Upset: An Embedded Tutorial. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumitra Bose, Vishwani D. Agrawal |
Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal |
Delay fault simulation with bounded gate delay mode. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal |
SPARTAN: a spectral and information theoretic approach to partial-scan. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumitra Bose, Vishwani D. Agrawal |
Delay Test Quality Evaluation Using Bounded Gate Delays. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nitin Yogi, Vishwani D. Agrawal |
Spectral RTL Test Generation for Microprocessors. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanlin Lu, Vishwani D. Agrawal |
Statistical Leakage and Timing Optimization for Submicron Process Variation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalyana R. Kantipudi, Vishwani D. Agrawal |
A Reduced Complexity Algorithm for Minimizing N-Detect Tests. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanlin Lu, Vishwani D. Agrawal |
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Transistor Sizing of Logic Gates to Maximize Input Delay Variability. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumitra Bose, Vishwani D. Agrawal |
Fault Coverage Estimation for Non-Random Functional Input Sequences. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Fei Hu, Vishwani D. Agrawal |
Input-specific dynamic power optimization for VLSI circuits. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
dynamic power optimization, glitch reduction, input specific |
| 1 | Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram |
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
Combinational automatic test pattern generation for acyclic sequential circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh |
A random access scans architecture to reduce hardware overhead. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanlin Lu, Vishwani D. Agrawal |
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal, Alok S. Doshi |
Concurrent Test Generation. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Fei Hu, Vishwani D. Agrawal |
Dual-transition glitch filtering in probabilistic waveform power estimation. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
dual-transition probability, dynamic power estimation, glitch filtering, probabilistic waveform simulation |
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Variable Input Delay CMOS Logic for Low Power Design. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Raja K. K. R. Sandireddy, Vishwani D. Agrawal |
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Fei Hu, Vishwani D. Agrawal |
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. |
J. Comput. Sci. Technol. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
1985 to 1987: My years with D&T. (PDF / PS) |
IEEE Design & Test of Computers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal |
On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
A Tuturial on the Emerging Nanotechnology Devices. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Editorial. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
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