Search results for "Vladimir Zolotov"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham	Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham	Testability driven statistical path selection.	DAC	2011	DBLP DOI BibTeX RDF
1	Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham	Path criticality computation in parameterized statistical timing analysis.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Vladimir Zolotov, Jinjun Xiong	Optimal statistical chip disposition.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chandu Visweswariah	Statistical Path Selection for At-Speed Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
1	Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah	Statistical Power Analysis for High-Performance Processors.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah, Peter A. Habitz	Optimal Test Margin Computation for At-Speed Structural Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov	Statistical ordering of correlated timing quantities and its application for path ranking.	DAC	2009	DBLP DOI BibTeX RDF	path ranking, statistical ordering, testing, correlation
1	Jinjun Xiong, Yiyu Shi, Vladimir Zolotov, Chandu Visweswariah	Statistical multilayer process space coverage for at-speed test.	DAC	2009	DBLP DOI BibTeX RDF	process space coverage, order statistics, path selection
1	Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong	Voltage binning under process variation.	ICCAD	2009	DBLP BibTeX RDF
1	Jiniun Xionq, Yiyu Shi, Vladimir Zolotov, Chandu Visweswariah	Pre-ATPG path selection for near optimal post-ATPG process space coverage.	ICCAD	2009	DBLP BibTeX RDF
1	Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah	Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power.	PATMOS	2008	DBLP DOI BibTeX RDF	Statistical power analysis
1	Ruiming Chen, Lizheng Zhang, Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong	Static timing: Back to our roots.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah, Peter A. Habitz	Optimal Margin Computation for At-Speed Test.	DATE	2008	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah	Incremental Criticality and Yield Gradients.	DATE	2008	DBLP DOI BibTeX RDF
1	Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chandu Visweswariah	Statistical path selection for at-speed test.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Vladimir Zolotov, Lei He	Robust Extraction of Spatial Correlation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah	Variation-aware performance verification using at-speed structural test and statistical timing.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Vladimir Zolotov, Jinjun Xiong, Soroush Abbaspour, David J. Hathaway, Chandu Visweswariah	Compact modeling of variational waveforms.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda	Impact of stress-induced backflow on full-chip electromigration risk assessment.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	Optimal placement of power-supply pads and pins.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Vladimir Zolotov, Lei He	Robust extraction of spatial correlation.	ISPD	2006	DBLP DOI BibTeX RDF	robust extraction, process variation, extraction, spatial correlation
1	Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah	Criticality computation in parameterized statistical timing.	DAC	2006	DBLP DOI BibTeX RDF	criticality probability, parametric variation, statistical timing
1	Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown	Optimization objectives and models of variation for statistical gate sizing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	parametric yield optimization, robust design
1	Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov	Circuit optimization using statistical static timing analysis.	DAC	2005	DBLP DOI BibTeX RDF
1	Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah	Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions.	DAC	2005	DBLP DOI BibTeX RDF
1	Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov	Gate sizing using incremental parameterized statistical timing analysis.	ICCAD	2005	DBLP BibTeX RDF
1	Amit Jain, David Blaauw, Vladimir Zolotov	Accurate delay computation for noisy waveform shapes.	ICCAD	2005	DBLP BibTeX RDF
1	Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov	Discrete Vt assignment and gate sizing using a self-snapping continuous formulation.	ICCAD	2005	DBLP BibTeX RDF
1	Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh	Pessimism reduction in crosstalk noise aware STA.	ICCAD	2005	DBLP BibTeX RDF
1	Aseem Agarwal, Vladimir Zolotov, David Blaauw	Statistical clock skew analysis considering intradie-process variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Postroute gate sizing for crosstalk noise reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda	A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.	ISQED	2004	DBLP DOI BibTeX RDF
1	Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	A stochastic approach To power grid analysis.	DAC	2004	DBLP DOI BibTeX RDF	Ldi/dt, IR drop, power supply networks
1	Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	Optimal placement of power supply pads and pins.	DAC	2004	DBLP DOI BibTeX RDF	pad optimization, pad placement
1	Dongwoo Lee, Vladimir Zolotov, David Blaauw	Static timing analysis using backward signal propagation.	DAC	2004	DBLP DOI BibTeX RDF	performance, Algorithms, reliability
1	Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer	False-Noise Analysis for Domino Circuits.	DATE	2004	DBLP DOI BibTeX RDF
1	Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda	Delay noise pessimism reduction by logic correlations.	ICCAD	2004	DBLP DOI BibTeX RDF
1	David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta	Static electromigration analysis for on-chip signal interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar	Fast on-chip inductance simulation using a precorrected-FFT method.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Aseem Agarwal, Vladimir Zolotov, David T. Blaauw	Statistical timing analysis using bounds and selective enumeration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta	Static Electromigration Analysis for Signal Interconnects.	ISQED	2003	DBLP DOI BibTeX RDF
1	Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Post-Route Gate Sizing for Crosstalk Noise Reduction.	ISQED	2003	DBLP DOI BibTeX RDF
1	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Computation and Refinement of Statistical Bounds on Circuit Delay.	DAC	2003	DBLP DOI BibTeX RDF
1	Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj	Post-route gate sizing for crosstalk noise reduction.	DAC	2003	DBLP DOI BibTeX RDF	crosstalk noise repair, gate sizing
1	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Statistical Timing Analysis Using Bounds.	DATE	2003	DBLP DOI BibTeX RDF
1	Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar	Table look-up based compact modeling for on-chip interconnect timing and noise analysis.	ISCAS	2003	DBLP DOI BibTeX RDF
1	D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel	SOI Transistor Model for Fast Transient Simulation.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Aseem Agarwal, David Blaauw, Vladimir Zolotov	Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	Vectorless Analysis of Supply Noise Induced Delay Variation.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Aseem Agarwal, David Blaauw, Vladimir Zolotov	Statistical Clock Skew Analysis Considering Intra-Die Process Variations.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov	False-noise analysis using logic implications.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	circuit logic, VLSI (very large scale integration), noise analysis
1	David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran	Slope propagation in static timing analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi	Inductance model and analysis methodology for high-speed on-chip interconnect.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh	Noise Injection and Propagation in High Performance Designs. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
1	Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh	False-Noise Analysis Using Resolution Method. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
1	Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj	Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .	DATE	2002	DBLP DOI BibTeX RDF
1	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Statistical timing analysis using bounds and selective enumeration.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
1	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Statistical timing analysis using bounds and selective enumeration.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
1	Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal	Worst case clock skew under power supply variations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	clock skew, power supply noise, clock network
1	Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar	A precorrected-FFT method for simulating on-chip inductance.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy	Noise propagation and failure criteria for VLSI designs.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj	A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.	ISQED	2001	DBLP DOI BibTeX RDF
1	Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo	Driver Modeling and Alignment for Worst-Case Delay Noise.	DAC	2001	DBLP DOI BibTeX RDF
1	Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao	Inductance 101: Analysis and Design Issues.	DAC	2001	DBLP DOI BibTeX RDF
1	Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov	False-Noise Analysis using Logic Implications.	ICCAD	2001	DBLP BibTeX RDF
1	Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju	Model and analysis for combined package and on-chip power grid simulation.	ISLPED	2000	DBLP DOI BibTeX RDF
1	David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang	On-chip inductance modeling.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
1	Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw	On-chip inductance modeling and analysis.	DAC	2000	DBLP DOI BibTeX RDF
1	Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov	ClariNet: a noise analysis tool for deep submicron design.	DAC	2000	DBLP DOI BibTeX RDF
1	David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda	Slope Propagation in Static Timing Analysis.	ICCAD	2000	DBLP BibTeX RDF

Publications of "Vladimir Zolotov" ( http://dblp.L3S.de/Authors/Vladimir_Zolotov )