Search results for "Wayne Burleson"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne Burleson	An architecture-independent instruction shuffler to protect against side-channel attacks.	TACO	2012	DBLP DOI BibTeX RDF
1	Jinwook Jang, Olivier Franza, Wayne Burleson	Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli	The combined effect of process variations and power supply noise on clock skew and jitter.	ISQED	2012	DBLP DOI BibTeX RDF
1	Jia Zhao, Russell Tessier, Wayne Burleson	Distributed sensor data processing for many-cores.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Vikram B. Suresh, Wayne P. Burleson	Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration.	ISQED	2012	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier	A Dedicated Monitoring Infrastructure for Multicore Processors.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	A 12.4μm2 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation.	ISQED	2011	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Jinwook Jang, Wayne Burleson	An arbiter based on-chip droop detector system.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Wayne Burleson, Yusuf Leblebici	Hardware security in VLSI.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Georg T. Becker, Ashwin Lakshminarasimhan, Lang Lin, Sudheendra Srivathsa, Vikram B. Suresh, Wayne Burleson	Implementing hardware Trojans: Experiences from a hardware Trojan challenge.	ICCD	2011	DBLP DOI BibTeX RDF
1	Krishna C. Chillara, Jinwook Jang, Wayne P. Burleson	Robust signaling techniques for through silicon via bundles.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne Burleson	Low-power sub-threshold design of secure physical unclonable functions.	ISLPED	2010	DBLP DOI BibTeX RDF	embedded system security, sub-threshold circuits, RFID, physical unclonable function
1	Basab Datta, Wayne Burleson	Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	tunable buffer, variability, NBTI, global-interconnect
1	Basab Datta, Wayne P. Burleson	Calibration of on-chip thermal sensors using process monitoring circuits.	ISQED	2010	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne P. Burleson	Circuit-level NBTI macro-models for collaborative reliability monitoring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	macro-models, on-chip sensors, calibration, NBTI
1	Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier	Thermal-aware voltage droop compensation for multi-core architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	monitor network-on-chip, thermal monitor, voltage emergency
1	Vikram B. Suresh, Wayne P. Burleson	Entropy Extraction in Metastability-based TRNG.	HOST	2010	DBLP DOI BibTeX RDF
1	Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier	Multicore soft error rate stabilization using adaptive dual modular redundancy.	DATE	2010	DBLP BibTeX RDF
1	Basab Datta, Wayne Burleson	Temperature effects on energy optimization in sub-threshold circuit design.	ISQED	2009	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	On temperature planarization effect of copper dummy fills in deep nanometer technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	Lang Lin, Markus Kasper, Tim Güneysu, Christof Paar, Wayne Burleson	Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering.	CHES	2009	DBLP DOI BibTeX RDF	Trojan Hardware, Trojan Side-Channel, Hardware Trojan Detection, Covert Channel, Side-Channel Analysis
1	Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier	A monitor interconnect and support subsystem for multicore processors.	DATE	2009	DBLP BibTeX RDF
1	Lang Lin, Wayne Burleson, Christof Paar	MOLES: Malicious off-chip leakage enabled by side-channels.	ICCAD	2009	DBLP BibTeX RDF
1	Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson	A security approach for off-chip memory in embedded microprocessor systems.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Daniel E. Holcomb, Wayne P. Burleson, Kevin Fu	Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne P. Burleson	Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sensor, interconnect, temperature, oscillator
1	Lang Lin, Wayne P. Burleson	Analysis and mitigation of process variation impacts on Power-Attack Tolerance.	DAC	2009	DBLP DOI BibTeX RDF	process variation, differential power analysis, Monte Carlo simulation, transistor sizing
1	Venkatesh Arunachalam, Wayne Burleson	Low-power clock distribution in a multilayer core 3d microprocessor.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	3D ic's, 3D processor architectures, clock grids
1	Basab Datta, Wayne Burleson	Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sensor, interconnect, temperature, oscillator
1	Lang Lin, Wayne Burleson	Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin	Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne P. Burleson	Temperature measurement in Content Addressable Memory cells using bias-controlled VCO.	SoCC	2008	DBLP DOI BibTeX RDF
1	Atul Maheshwari, Wayne Burleson	Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson	High-efficiency protection solution for off-chip memory in embedded systems.	ERSA	2007	DBLP BibTeX RDF
1	Sheng Xu, Ibis Benito, Wayne P. Burleson	Thermal Impacts on NoC Interconnects.	NOCS	2007	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne P. Burleson	Low power on-chip thermal sensors based on wires.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Romain Vaslin, Guy Gogniat, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson	Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.	ReCoSoC	2007	DBLP BibTeX RDF
1	Lilian Bossuet, Guy Gogniat, Wayne Burleson	Dynamically configurable security for SRAM FPGA bitstreams.	IJES	2006	DBLP DOI BibTeX RDF
1	Guy Gogniat, Tilman Wolf, Wayne Burleson	Reconfigurable Security Support for Embedded Systems.	HICSS	2006	DBLP DOI BibTeX RDF
1	Jeongseon Euh, Jeevan Chittamuru, Wayne Burleson	Power-Aware 3D Computer Graphics Rendering.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	low-power, reconfigurable, texture mapping, 3D Graphics, shading
1	Guy Gogniat, Wayne Burleson, Lilian Bossuet	Configurable Computing for High-Security/High-Performance Ambient Systems.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Wayne Burleson, Sheng Xu	Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats.	MSE	2005	DBLP DOI BibTeX RDF
1	Vishak Venkatraman, Wayne Burleson	Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations.	ISQED	2005	DBLP DOI BibTeX RDF
1	Jinwook Jang, Sheng Xu, Wayne Burleson	Jitter in Deep Sub-Micron Interconnect.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson	Sensing Design Issues in Deep Submicron CMOS SRAMs.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Vishak Venkatraman, Wayne Burleson	Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris	Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	test, debug, SoC, nondeterminism, GALS, globally asynchronous locally synchronous
1	Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson	An energy-aware active smart card.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson	A reconfigurable, power-efficient adaptive Viterbi decoder.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Atul Maheshwari, Wayne Burleson, Russell Tessier	Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Prashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier, Dennis Goeckel	Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	VLSI, motion estimation, digital signal processing, MPEG, power-aware
1	Vishak Venkatraman, Atul Maheshwari, Wayne Burleson	Mitigating static power in current-sensed interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	interconnect circuits, static power, self-timed systems
1	Lilian Bossuet, Guy Gogniat, Wayne Burleson	Dynamically Configurable Security for SRAM FPGA Bitstreams.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson	NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods.	SLIP	2004	DBLP DOI BibTeX RDF	on-chip, spice-based, network-on-chip, interconnects, signaling
1	Atul Maheshwari, Wayne P. Burleson	Differential current-sensing for on-chip interconnects.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris	Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s.	DATE	2004	DBLP DOI BibTeX RDF
1	Andrew Laffely, Wayne Burleson	Using System On-A-Chip As A Vehicle For VLSI Design Education.	MSE	2003	DBLP DOI BibTeX RDF
1	Srividya Srinivasaraghavan, Wayne Burleson	Interconnect Effort - A Unification of Repeater Insertion and Logical Effort.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Aiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier	A hybrid adiabatic content addressable memory for ultra low-power applications.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	adiabatic switching, ultra-low power, energy recovery
1	Atul Maheshwari, Wayne Burleson	Repeater and current-sensing hybrid circuits for on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	interconnect circuits, delay, power, area
1	Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas Anand, Andrew Laffely, Jean Luc Philippe	Targeting Tiled Architectures in Design Exploration.	IPDPS	2003	DBLP DOI BibTeX RDF
1	Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson	Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.	ICIP	2003	DBLP BibTeX RDF
1	Atul Maheshwari, Israel Koren, Wayne Burleson	Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits.	DFT	2003	DBLP DOI BibTeX RDF
1	Atul Maheshwari, Wayne Burleson, Russell Tessier	Trading off Reliability and Power-Consumption in Ultra-low Power Systems. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
1	Jeongseon Euh, Jeevan Chittamuru, Wayne Burleson	A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics.	PACS	2002	DBLP DOI BibTeX RDF
1	Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson	A dynamically reconfigurable adaptive viterbi decoder.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
1	Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson	Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Wayne Burleson, Naresh R. Shanbhag	Guest Editorial: Reconfigurable Signal Processing Systems.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF
1	Russell Tessier, Wayne Burleson	Reconfigurable Computing for Digital Signal Processing: A Survey.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	FPGA, survey, signal processing, reconfigurable computing
1	Ankireddy Nalamalpu, Wayne Burleson	Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.	ISPD	2001	DBLP DOI BibTeX RDF	methodology, timing, interconnect, buffering
1	Wayne Burleson, Prashant Jain, Subramanian Venkatraman	Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT.	Workshop on Digital and Computational Video	2001	DBLP DOI BibTeX RDF
1	Elias S. Manolakos, Wayne Burleson	Guest Editor's Introduction.	VLSI Signal Processing	2000	DBLP DOI BibTeX RDF
1	Jeongseon Euh, Wayne Burleson	Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering.	PACS	2000	DBLP DOI BibTeX RDF
1	J. Peden, Wayne Burleson, C. Leonardo	The Multimedia Online Collaboration Architecture: Tools to Enable Distance Learning.	IEEE International Conference on Multimedia and Expo (II)	2000	DBLP BibTeX RDF
1	Andrés D. García, Jean-Luc Danger, Wayne P. Burleson	Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.	FPGA	2000	DBLP DOI BibTeX RDF
1	S. R. Park, Wayne Burleson	Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures.	FPGA	1999	DBLP DOI BibTeX RDF
1	Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems	The spring scheduling coprocessor: a scheduling accelerator.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Andrés D. García, Wayne P. Burleson, Jean-Luc Danger	Power Modelling in Field Programmable Gate Arrays (FPGA).	FPL	1999	DBLP DOI BibTeX RDF
1	Bongjin Jung, Wayne P. Burleson	Performance optimization of wireless local area networks through VLSI data compression.	Wireless Networks	1998	DBLP DOI BibTeX RDF
1	Bongjin Jung, Wayne P. Burleson	Efficient VLSI for Lempel-Ziv compression in wireless data communication networks.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu	Wave-pipelining: a tutorial and research survey.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Wayne P. Burleson, Konstantinos Konstantinides	Guest Editors' Introduction.	VLSI Signal Processing	1998	DBLP DOI BibTeX RDF
1	Bongjin Jung, Wayne P. Burleson	Vlsi Array Architectures for Pyramid Vector Quantization.	VLSI Signal Processing	1998	DBLP DOI BibTeX RDF
1	Yongjin Jeong, Wayne P. Burleson	VLSI array algorithms and architectures for RSA modular multiplication.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Wayne P. Burleson	Low-power encodings for global communication in CMOS VLSI.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Wayne P. Burleson	Two dimensional codes for low power.	ISLPED	1996	DBLP DOI BibTeX RDF
1	Zheng Zhou, Wayne Burleson	Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions.	DAC	1995	DBLP DOI BibTeX RDF	high-level synthesis systems-level design aids, design verification
1	Yongjin Jeong, Wayne Burleson	High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding.	ISCAS	1995	DBLP BibTeX RDF
1	Mircea R. Stan, Wayne P. Burleson	Bus-invert coding for low-power I/O.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
1	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
1	Wayne Burleson	Using Regular Array Methods for DSP Module Synthesis.	HICSS	1994	DBLP BibTeX RDF
1	Bongjin Jung, Wayne Burleson	A VLSI Systolic Array Architecture for Lempel-Ziv-Based Data Compression.	ISCAS	1994	DBLP BibTeX RDF
1	Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski	Forum: Wave-pipelining: Is it Practical?	ISCAS	1994	DBLP BibTeX RDF
1	Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen	Analog VLSI for robot path planning.	VLSI Signal Processing	1994	DBLP DOI BibTeX RDF
1	Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems, Wayne Burleson, Jason Ko	The Spring Scheduling Co-Processor: Design, Use, and Performance.	IEEE Real-Time Systems Symposium	1993	DBLP BibTeX RDF
1	J. David Narkiewicz, Wayne Burleson	Rank-order Filtering Algorithms: A Comparison of VLSI Implementations.	ISCAS	1993	DBLP BibTeX RDF
1	Wayne Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems	The Spring Scheduling Co-Processor: A Scheduling Accelerator.	ICCD	1993	DBLP BibTeX RDF

Publications of Wayne Burleson Wayne P. Burleson ( http://dblp.L3S.de/Authors/Wayne_Burleson )