Search results for "Wayne Luk"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ka Fai Cedric Yiu, Yao Lu, Chun Hok Ho, Wayne Luk, Jiaquan Huo, Sven Nordholm	Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device.	Digital Signal Processing	2012	DBLP DOI BibTeX RDF
1	Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar	FISH: Fast Instruction SyntHesis for Custom Processors.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Anson H. T. Tse, David B. Thomas, Wayne Luk	Design Exploration of Quadrature Methods in Option Pricing.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides	Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms.	Signal Processing Systems	2012	DBLP DOI BibTeX RDF
1	José Gabriel F. Coutinho, Tiago Carvalho, Sérgio Durand, João M. P. Cardoso, Ricardo Nobre, Pedro C. Diniz, Wayne Luk	Experiments with the LARA aspect-oriented approach.	AOSD (Companion)	2012	DBLP DOI BibTeX RDF
1	João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Wayne Luk, Ricardo Nobre, Pedro C. Diniz, Zlatko Petrov	LARA: an aspect-oriented programming language for embedded systems.	AOSD	2012	DBLP DOI BibTeX RDF
1	Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas	A mixed precision Monte Carlo methodology for reconfigurable accelerator systems.	FPGA	2012	DBLP DOI BibTeX RDF
1	Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk	Optimising Performance of Quadrature Methods with Reduced Precision.	ARC	2012	DBLP DOI BibTeX RDF
1	Stewart Denholm, Kuen Hung Tsoi, Peter Pietzuch, Wayne Luk	Efficient Communication for FPGA Clusters.	ARC	2012	DBLP DOI BibTeX RDF
1	Qiang Liu, Wayne Luk	Heterogeneous Systems for Energy Efficient Scientific Computing.	ARC	2012	DBLP DOI BibTeX RDF
1	Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston	Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations.	ARC	2012	DBLP DOI BibTeX RDF
1	Kuen Hung Tsoi, Wayne Luk	Power profiling and optimization for heterogeneous multi-core systems.	SIGARCH Computer Architecture News	2011	DBLP DOI BibTeX RDF
1	William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, O. Mencer	Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes	A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert	Design Optimizations for Tiled Partially Reconfigurable Systems.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	An Analytical Model Relating FPGA Architecture to Logic Density and Depth.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev	Power adaptive computing system design in energy harvesting environment.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Adrien Le Masle, Wayne Luk, Csaba Andras Moritz	Parametrized hardware architectures for the Lucas primality test.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Xin Yu Niu, Kuen Hung Tsoi, Wayne Luk	Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking.	FPL	2011	DBLP DOI BibTeX RDF	FPGA Cluster, Wireless network
1	Qiwei Jin, Wayne Luk, David B. Thomas	Unifying Finite Difference Option-Pricing for Hardware Acceleration.	FPL	2011	DBLP DOI BibTeX RDF	FPGA, Framework, Finance, Finite Difference, Option Pricing
1	Adrien Le Masle, Gary Chun Tak Chow, Wayne Luk	Constant power reconfigurable computing.	FPT	2011	DBLP DOI BibTeX RDF
1	Kong Woei Susanto, Wayne Luk	Automating formal verification of customized soft-processors.	FPT	2011	DBLP DOI BibTeX RDF
1	Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj	A framework for FPGA acceleration of large graph problems: Graphlet counting case study.	FPT	2011	DBLP DOI BibTeX RDF
1	Chi Wai Yu, Fred Cox, Wayne Luk, Ray C. C. Cheung	Hydrate: Hybrid Reconfigurable Architecture Expressions.	FPT	2011	DBLP DOI BibTeX RDF
1	Qiang Liu, Wayne Luk	Objective-driven workload allocation in heterogeneous computing systems.	FPT	2011	DBLP DOI BibTeX RDF
1	Stewart Denholm, Kuen Hung Tsoi, Peter Pietzuch, Wayne Luk	CusComNet: A customisable network for reconfigurable heterogeneous clusters.	ASAP	2011	DBLP DOI BibTeX RDF
1	Gary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Heng Wai Leong	Mixed Precision Processing in Reconfigurable Systems.	FCCM	2011	DBLP DOI BibTeX RDF
1	Qiwei Jin, Wayne Luk, David B. Thomas	On Comparing Financial Option Price Solvers on FPGA.	FCCM	2011	DBLP DOI BibTeX RDF
1	Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk	A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk	FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design.	ARC	2011	DBLP DOI BibTeX RDF
1	Tobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston	Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk	Efficient reconfigurable design for pricing asian options.	SIGARCH Computer Architecture News	2010	DBLP DOI BibTeX RDF
1	Kuen Hung Tsoi, Anson H. T. Tse, Peter Pietzuch, Wayne Luk	Programming framework for clusters with heterogeneous accelerators.	SIGARCH Computer Architecture News	2010	DBLP DOI BibTeX RDF
1	Koen Bertels, Vlad Mihai Sima, Yana Yankova, Georgi Kuzmanov, Wayne Luk, José Gabriel F. Coutinho, Fabrizio Ferrandi, Christian Pilato, Marco Lattuada, Donatella Sciuto, Andrea Michelotti	HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen	Benchmarking and evaluating reconfigurable architectures targeting the mobile domain.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes	Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	video, performance measures, reconfigurable hardware, Graphics processors, real-time and embedded systems, signal processing systems
1	Haohuan Fu, Oskar Mencer, Wayne Luk	FPGA Designs with Optimized Logarithmic Arithmetic.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	general, computer arithmetic, numerical analysis, Reconfigurable hardware, computer systems organization, special-purpose and application-based systems, mathematics of computing
1	Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa	Power Characterisation for Fine-Grain Reconfigurable Fabrics.	Int. J. Reconfig. Comp.	2010	DBLP DOI BibTeX RDF
1	Yuet Ming Lam, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk	Multiloop Parallelisation Using Unrolling and Fission.	Int. J. Reconfig. Comp.	2010	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	Wave-pipelined intra-chip signaling for on-FPGA communications.	Integration	2010	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk	FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers.	FPL	2010	DBLP DOI BibTeX RDF
1	Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk	Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options.	FPL	2010	DBLP DOI BibTeX RDF
1	Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Heng Wai Leong	A Karatsuba-Based Montgomery Multiplier.	FPL	2010	DBLP DOI BibTeX RDF
1	Stephen Wray, Wayne Luk, Peter Pietzuch	Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine.	FPL	2010	DBLP DOI BibTeX RDF
1	Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides	Customizable Composition and Parameterization of Hardware Design Transformations.	DSD	2010	DBLP DOI BibTeX RDF
1	Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk	Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters.	FPT	2010	DBLP DOI BibTeX RDF
1	Brahim Betkaoui, David B. Thomas, Wayne Luk	Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing.	FPT	2010	DBLP DOI BibTeX RDF
1	Vinay Sriram, David Cox, Kuen Hung Tsoi, Wayne Luk	Towards an embedded biologically-inspired machine vision processor.	FPT	2010	DBLP DOI BibTeX RDF
1	Qiang Liu, Tim Todman, Kuen Hung Tsoi, Wayne Luk	Convex models for accelerating applications on FPGA-based clusters.	FPT	2010	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk	An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers.	ASAP	2010	DBLP DOI BibTeX RDF
1	Adrien Le Masle, Wayne Luk	Design space exploration of parametric pipelined designs.	ASAP	2010	DBLP DOI BibTeX RDF
1	Stephen Wray, Wayne Luk, Peter Pietzuch	Exploring algorithmic trading in reconfigurable hardware.	ASAP	2010	DBLP DOI BibTeX RDF
1	Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides	A Scripting Engine for Combining Design Transformations.	FCCM	2010	DBLP DOI BibTeX RDF
1	Tobias Becker, Wayne Luk, Peter Y. K. Cheung	Energy-Aware Optimisation for Run-Time Reconfiguration.	FCCM	2010	DBLP DOI BibTeX RDF
1	Kuen Hung Tsoi, Wayne Luk	Axel: a heterogeneous cluster with FPGAs and GPUs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, heterogeneous cluster
1	Qiang Liu, Tim Todman, Wayne Luk	Combining optimizations in automated low power design.	DATE	2010	DBLP BibTeX RDF
1	Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung	Exploration of hardware sharing for image encoders.	DATE	2010	DBLP BibTeX RDF
1	Tobias Becker, Markus Koester, Wayne Luk	Automated placement of reconfigurable regions for relocatable modules.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Adrien Le Masle, Wayne Luk, Jared Eldredge, Kris Carver	Parametric Encryption Hardware Design.	ARC	2010	DBLP DOI BibTeX RDF
1	Haohuan Fu, William G. Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk	Accelerating Seismic Computations Using Customized Number Representations on FPGAs.	EURASIP J. Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk	High-throughput one-dimensional median and weighted median filters on FPGA.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton	Floating-Point FPGA: Architecture and Modeling.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor	Hierarchical Segmentation for Hardware Function Evaluation.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope	Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models.	TRETS	2009	DBLP DOI BibTeX RDF
1	Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	Modeling post-techmapping and post-clustering FPGA circuit depth.	FPL	2009	DBLP DOI BibTeX RDF
1	Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides	Optimising designs by combining model-based and pattern-based transformations.	FPL	2009	DBLP DOI BibTeX RDF
1	Qiwei Jin, David B. Thomas, Wayne Luk	Exploring reconfigurable architectures for explicit finite difference option pricing models.	FPL	2009	DBLP DOI BibTeX RDF
1	Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson	Harnessing Human Computation Cycles for the FPGA Placement Problem.	ERSA	2009	DBLP BibTeX RDF
1	Julien Lamoureux, Tony Field, Wayne Luk	Accelerating a Virtual Ecology Model with FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF
1	Andreas Fidjeland, Etienne B. Roesch, Murray Shanahan, Wayne Luk	NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs.	ASAP	2009	DBLP DOI BibTeX RDF
1	Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen	Benchmarking Reconfigurable Architectures in the Mobile Domain.	FCCM	2009	DBLP DOI BibTeX RDF	Mobile Domain, FPGA, Low Power, Reconfigurable Architectures
1	Anson H. T. Tse, David B. Thomas, Wayne Luk	Accelerating Quadrature Methods for Option Valuation.	FCCM	2009	DBLP DOI BibTeX RDF	Option Valuation, Finance, Option pricing, Quadrature
1	David B. Thomas, Wayne Luk	FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, spiking neural networks
1	David B. Thomas, Lee W. Howes, Wayne Luk	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.	FPGA	2009	DBLP DOI BibTeX RDF	mppa, fpga, monte-carlo, random numbers, gpu
1	Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann	Design optimizations to improve placeability of partial reconfiguration modules.	DATE	2009	DBLP BibTeX RDF
1	Philip G. Potter, Wayne Luk, Peter Y. K. Cheung	Partition-based exploration for reconfigurable JPEG designs.	DATE	2009	DBLP BibTeX RDF
1	Tobias Becker, Wayne Luk, Peter Y. K. Cheung	Parametric Design for Reconfigurable Software-Defined Radio.	ARC	2009	DBLP DOI BibTeX RDF
1	Kong Woei Susanto, Tim Todman, José Gabriel F. Coutinho, Wayne Luk	Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation.	SOFSEM	2009	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Wayne Luk, Jakub Szefer, Ruby B. Lee	Tuning instruction customisation for reconfigurable system-on-chip.	SoCC	2009	DBLP DOI BibTeX RDF
1	Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William G. Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong	A high-level compilation toolchain for heterogeneous systems.	SoCC	2009	DBLP DOI BibTeX RDF
1	Gareth W. Morris, David B. Thomas, Wayne Luk	FPGA Accelerated Low-Latency Market Data Feed Processing.	Hot Interconnects	2009	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A DP-network for optimal dynamic routing in network-on-chip.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	optimal and sub-optimal routing, dynamic programming, network-on-chip, adaptive routing
1	Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung	Custom parallel caching schemes for hardware-accelerated image compression.	J. Real-Time Image Processing	2008	DBLP DOI BibTeX RDF
1	Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor	Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Approximation, Interpolation, VLSI Systems, Algorithms implemented in hardware
1	Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk	CHIPS: Custom Hardware Instruction Processor Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units.	Int. J. Reconfig. Comp.	2008	DBLP DOI BibTeX RDF
1	Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker Dulay, Emil C. Lupu, Geoffrey Brown	Reconfigurable Architecture for Network Flow Analysis.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Wayne Luk, Yvon Savaria, Oskar Mencer	Guest Editorial: 20 Years of ASAP.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF
1	Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.	TRETS	2008	DBLP DOI BibTeX RDF	Field programmable gate array, system-on-chip, integrated circuit, silicon debug
1	David B. Thomas, Wayne Luk	Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware.	TRETS	2008	DBLP DOI BibTeX RDF	FPGA, Random numbers, multivariate Gaussian distribution
1	Duncan A. Buell, Wayne Luk	Introduction.	TRETS	2008	DBLP DOI BibTeX RDF
1	William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer	Reconfigurable design with clock gating.	ICSAMOS	2008	DBLP DOI BibTeX RDF
1	Ben Cope, Peter Y. K. Cheung, Wayne Luk	Systematic design space exploration for customisable multi-processor architectures.	ICSAMOS	2008	DBLP DOI BibTeX RDF
1	Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa	Towards benchmarking energy efficiency of reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
1	Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong	Mapping and scheduling with task clustering for heterogeneous computing systems.	FPL	2008	DBLP DOI BibTeX RDF
1	David B. Thomas, Wayne Luk	Sampling from the exponential distribution using independent Bernoulli variates.	FPL	2008	DBLP DOI BibTeX RDF
1	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton	Rapid estimation of power consumption for hybrid FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
1	Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk	An analytical model describing the relationships between logic architecture and FPGA density.	FPL	2008	DBLP DOI BibTeX RDF
1	Markus Koester, Wayne Luk, Geoffrey Brown	A hardware compilation flow for instance-specific VLIW cores.	FPL	2008	DBLP DOI BibTeX RDF
1	Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk	Smart Enumeration: A Systematic Approach to Exhaustive Search.	PATMOS	2008	DBLP DOI BibTeX RDF

Publications of "Wayne Luk" ( http://dblp.L3S.de/Authors/Wayne_Luk )