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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 41 occurrences of 29 keywords
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Results
Found 45 publication records. Showing 45 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ramon Canal, Antonio Rubio, A. Asenov, A. Brown, Miguel Miranda, Paul Zuber, Antonio González, Xavier Vera |
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.  |
Procedia CS  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González |
Implementing End-to-End Register Data-Flow Continuous Self-Test. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
end-to-end protection, Online testing, degradation, design errors, control logic |
| 1 | Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González |
Accelerating microprocessor silicon validation by exposing ISA diversity. |
MICRO |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, A. Biswas, Xavier Vera |
Architectures for online error detection and recovery in multicore processors. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Javier Carretero, Jaume Abella, Xavier Vera, Pedro Chaparro |
Control-Flow Recovery Validation Using Microarchitectural Invariants. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nivard Aymerich, A. Asenov, A. Brown, Ramon Canal, B. Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, P. Pouyan, Tanausu Ramirez, Antonio Rubio, I. Vatajelu, Xavier Vera, X. Wang, Paul Zuber |
New reliability mechanisms in memory design for sub-22nm technologies. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Carretero, Xavier Vera, Jaume Abella, Tanausu Ramirez, Matteo Monchiero, Antonio González |
Hardware/software-based diagnosis of load-store queues using expandable activity logs. |
HPCA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González |
Design of complex circuits using the Via-Configurable transistor array regular layout fabric. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella |
Microarchitectural Online Testing for Failure Detection in Memory Order Buffers. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
memory order buffer, error detection, soft errors, microarchitecture, defects, Online testing, control logic |
| 1 | Jaume Abella, Xavier Vera |
Electromigration for microarchitects. |
ACM Comput. Surv. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González |
MT-SBST: Self-test optimization in multithreaded multicore architectures. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González |
VCTA: A Via-Configurable Transistor Array regular fabric. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera |
The split register file. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González |
High-Performance low-vcc in-order core. |
HPCA |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González |
Reducing Soft Errors through Operand Width Aware Policies. |
IEEE Trans. Dependable Sec. Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Jaume Abella, Javier Carretero, Antonio González |
Selective replication: A lightweight technique for soft errors. |
ACM Trans. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González |
End-to-end register data-flow continuous self-test. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
end-to-end protection, online testing, degradation, design errors, control logic |
| 1 | Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González |
Low Vccmin fault-tolerant cache with highly predictable performance. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
Vccmin, cache, faults, predictable performance |
| 1 | Xavier Vera |
DFx for massively multiprocessors. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González |
Online error detection and correction of erratic bits in register files. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz |
Refueling: Preventing Wire Degradation due to Electromigration. |
IEEE Micro |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella |
On-line Failure Detection in Memory Order Buffers. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González |
On-Line Failure Detection and Confinement in Caches. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera |
Issue system protection mechanisms. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Björn Lisper, Jingling Xue |
Data cache locking for tight timing calculations. |
ACM Trans. Embedded Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
data cache analysis, embedded systems, Worst-case execution time, safety critical systems |
| 1 | Jaume Abella, Xavier Vera, Antonio González |
Penelope: The NBTI-Aware Processor. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Jaume Abella |
Surviving to Errors in Multi-Core Environments. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González |
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González |
Exploiting Narrow Values for Soft Error Tolerance. |
Computer Architecture Letters |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin |
Impact of Parameter Variations on Circuits and Microarchitecture. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
variation-tolerant design, impact of VLSI on system design, processor architectures, performance and reliability |
| 1 | Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González |
Empowering a helper cluster through data-width aware instruction selection policies. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle |
IATAC: a smart predictor to turn-off L2 cache lines. |
TACO |
2005 |
DBLP DOI BibTeX RDF |
turning off cache lines, low power, Cache memories, L2 cache |
| 1 | Xavier Vera, Jaume Abella, Josep Llosa, Antonio González |
An accurate cost model for guiding data locality transformations. |
ACM Trans. Program. Lang. Syst. |
2005 |
DBLP DOI BibTeX RDF |
genetic algorithms, Cache memories, tiling, padding |
| 1 | Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González |
Variable-Based Multi-module Data Caches for Clustered VLIW Processors. |
IEEE PACT |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingling Xue, Xavier Vera |
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
performance evaluation, analytical modeling, cache memories, data locality, Modeling techniques |
| 1 | Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González |
A fast and accurate framework to analyze and optimize cache memory behavior. |
ACM Trans. Program. Lang. Syst. |
2004 |
DBLP DOI BibTeX RDF |
optimization, sampling, Cache memories |
| 1 | Xavier Vera, Jaume Abella, Antonio González, Josep Llosa |
Optimizing Program Locality Through CMEs and GAs. |
IEEE PACT |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Qingguang Huang, Jingling Xue, Xavier Vera |
Code Tiling for Improving the Cache Performance of PDE Solvers. |
ICPP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Björn Lisper, Jingling Xue |
Data Caches in Multitasking Hard Real-Time Systems. |
RTSS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Björn Lisper, Jingling Xue |
Data cache locking for higher program predictability. |
SIGMETRICS |
2003 |
DBLP DOI BibTeX RDF |
data cache analysis, worst-case execution time |
| 1 | Xavier Vera, Josep Llosa, Antonio González |
Near-Optimal Padding for Removing Conflict Misses. |
LCPC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Jingling Xue |
Let's Study Whole-Program Cache Behaviour Analytically. |
HPCA |
2002 |
DBLP DOI BibTeX RDF |
Cache Miss Equations, Performance Evaluation, Data Locality, Cache Performance |
| 1 | Jaume Abella, Antonio González, Josep Llosa, Xavier Vera |
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. |
ICPP Workshops |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa |
Optimizing cache miss equations polyhedra. |
SIGARCH Computer Architecture News |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo |
A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). |
Euro-Par |
2000 |
DBLP DOI BibTeX RDF |
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